NON-FINAL OFFICE ACTION
Acknowledgements
1. This non-final Office Action addresses broadening reissue U.S. Application No. 18/812,400 (“instant application”). Examiners find the actual filing date of the instant application is August 22, 2024.
2. The instant application is a broadening reissue application of U.S. Patent No. 10,720,558, (“‘558 Patent”) issued Jul. 21, 2020. The ‘558 Patent was filed on Dec. 19. 2017 as U.S. Application No. 15/846,563 (“563 Application”), titled “LIGHT EMITTING DIODE CHIP AND APPARATUS WITH REDUCED SCREEN DEFECT”.
3. Examiners do not find any certificates of correction, ongoing/previous proceedings before the Office, or current ongoing litigation involving the ‘558 Patent.
4. Examiners find U.S. App. No. 17/869,553, now RE50146 (“R1”) issued Sept. 24, 2024 and U.S. App. No. 18/811,663 (“R2”), now abandoned, which are both reissue applications for the ‘558 Patent.
5. The ‘558 Patent issued with claims 1-14 (“Patented Claims”). In the preliminary amendment filed August 22, 2024 ("AUGUST 2024 CLAIM AMENDMENTS"), claims 8-14 are cancelled and claims 15-44 are added.
6. Claims 1-7 and 15-44 are pending.
Priority Claims
7. Examiners find the instant application is claiming foreign priority under 35 U.S.C. 35 U.S.C. § 119(a)-(d) to KR 10-2016-0174731 filed Dec. 20, 2016.
8. The presumed effective U.S. filing date of the instant application is Dec. 19, 2017.
Specification Objections
9. The amendment to the specification is objected to because it does not comply with the marking requirements of 37 CFR 1.173. Specifically, matter is omitted via strikethrough rather than via brackets.
In addition, the amendment is objected to because it does not contain a cross-reference to the now abandoned application, R2. CORRECTION IS REQUIRED.
Claim Objections
10. The AUGUST 2024 CLAIM AMENDMENTS are objected to because they do not comply with the marking requirements of 37 CFR 1.173. Specifically, amendments are made with respect to the patent. Here, claims 15-44 are new with respect to the patent. As such, they should be underlined. CORRECTION IS REQUIRED.
§251 Rejections
11. Claims 1-7 and 15-44 are rejected 35 U.S.C. 251, in that the reissue application is not correcting an error in the original patent, because original claims 1-7 would be superseded by the reissuance of claims 1-7 in the other reissue application.
It is noted that the same claim of the patent cannot be presented for examination in more than one reissue application, as a pending claim, in either its original or amended versions. If a patent claim is presented in one of the reissue applications of a reissue application "family," as a pending claim, then that patent claim must be presented as a canceled claim in all the other reissue applications of that family. Once a claim in the patent has been reissued, it does not exist in the original patent; thus, it cannot be reissued from the original patent in another reissue application. If the same claim of the patent, e.g., patent claim 1 is presented for examination in more than one of the reissue applications, in different amended versions, the following rejections should be made in the reissue applications with that patent claim. See MPEP §1451.
12. Claims 1-7 and 15-44 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251 as set forth above. See 37 CFR 1.175.
Specifically, the error is described as follows:
PNG
media_image1.png
96
706
media_image1.png
Greyscale
Patent claim 1, however, is as follows:
PNG
media_image2.png
342
414
media_image2.png
Greyscale
In other words, Examiners do not find a recitation of “a pixel electrode…electrically connected with…each of the first and second light emitting diodes” in patent claim 1, which Applicants allege is unduly narrowing. As such, the statement does not allege an error upon which this reissue is based because the alleged error is not found in patent claim 1. Thus, the reissue declaration is defective.
Examiners remind Applicants that the error stated as the basis for this reissue must be a different error than an error corrected in R1 or alternatively, if the same error is corrected in the instant application, the same error must be corrected in a different way to support this application. See MPEP §1414.
Examiners suggest the following language for the statement of the error:
--Claim ** has been broadened by removing the limitation “***,” which was unduly narrowing.—
Claim Rejections - 35 USC § 112
13. Claims 1-7 and 15-44 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Specifically, independent claim 1 recites “a light emitting diode includes a first electrode and a second,” which is indefinite because it is unclear whether “a second” is a “second electrode” or alternatively, “a second light emitting diode.”
Also, “the light emitting diode chip” does not have an antecedent basis.
Claims 2-7 and 15-44 are rejected based on their dependence upon rejected claim 1.
In the interest of compact prosecution, the indefinite phrase recites “a light emitting diode includes a first electrode and a second” will be interpreted as recites “a light emitting diode includes a first electrode and a second electrode.”
14. Claims 1-7 are rejected under 35 U.S.C. 112(b) as being indefinite because the invention of claims 1-7 is not particularly pointed out and distinctly claimed. Claims 1-7 present one coverage in divisional reissue application X and another in the present reissue application. This is inconsistent.
Double Patenting
15. Claims 1-7 and 16-441 are rejected on the ground of nonstatutory double patenting as being unpatentable over the following respective claims of R1. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are merely broader than the claims of the conflicting application.
Instant Application
Conflicting R1
1. A LED display apparatus comprising:
a pixel including a driving thin film transistor on a substrate;
a 1st planarization layer covering the pixel;
a LED include a 1st electrode and a 2nd;
a 2nd planarization layer covering at least a part of the 1st planarization layer or the LED;
a pixel electrode provided on the 2nd planarization layer and electrically connected to the driving thin film transistor and the 1st electrode; and
a common electrode provided on the 2nd planarization layer and electrically connected to the 2nd electrode,
wherein the LED chip includes a 1st LED and a 2nd LED in parallel on a semiconductor substrate in parallel.
1. A LED display apparatus comprising:
a driving TFT on a substrate;
a 1st planarization layer on the driving TFT;
a LED chip including a 1st LED and a 2nd LED,
wherein each of the 1st and 2nd LEDs includes a 1st pad and a 2nd pad;
a 2nd planarization layer covering the 1st planarization layer and the LED chip;
a pixel electrode provided on the 2nd planarization layer and electrically connected with the driving TFT and the 1st pad of each of the 1st and 2nd LEDs; and
a common electrode provided on the 2nd planarization layer and electrically connected to the 2nd pad of each of the 1st and 2nd LEDs.
2. The LED display apparatus of claim 1,
wherein each of the 1st LED and the 2nd LED includes:
a 1st semiconductor layer on the semiconductor substrate;
an active layer on the 1st semiconductor layer;
a 2nd semiconductor layer on the active layer;
a 1st pad on the 2nd semiconductor layer; and
a 2nd pad on the 1st semiconductor layer.
2. The LED display apparatus of claim 1,
wherein each of the 1st and 2nd LEDs further includes:
a 1st semiconductor layer;
an active layer on the 1st semiconductor layer; and
a 2nd semiconductor layer on the active layer,
wherein the 1st pad is disposed on the 2nd semiconductor layer, and
wherein the 2nd pad is disposed on the 1st semiconductor layer.
3. The LED display apparatus of claim 2, wherein the LED further includes
an insulating layer covering the 1st LED and the 2nd LED,
the 1st electrode is commonly connected to the 1st pad of each of the 1st LED and the 2nd LED through a 1st pad contact hole in the insulating layer, and
the 2nd electrode is commonly connected to the 2nd pad through each of the 1st LED and the 2nd LED through a 2nd pad contact hole in the insulating layer.
3. The LED display apparatus of claim 2,
wherein the LED chip further includes
an insulating layer covering the 1st and 2nd LEDs,
the pixel electrode is commonly connected to the 1st pad of each of the 1st and 2nd LEDs through a 1st pad contact hole in the insulating layer, and
the common electrode is commonly connected to the 2nd pad of each of the 1st and 2nd LEDs through a 2nd pad contact hole in the insulating layer.
4. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein the pixel electrode is provided on an upper surface of the 1st planarization layer and electrically connected to the driving thin film transistor and the 1st electrode, and
the common electrode is provided on the upper surface of the 1st planarization layer and electrically connected to the common power line and the 2nd electrode.
4. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 1st planarization layer, and
the common electrode is provided on the 1st planarization layer and electrically connected to the common power line.
5. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 2nd planarization layer and electrically connected to the driving thin film transistor and the 1st electrode, and
the common electrode is provided on the upper surface of the 2nd planarization layer and electrically connected to the common power line and the 2nd electrode.
5. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein the pixel electrode is provided on an upper surface of the 2nd planarization layer, and
wherein the common electrode is provided on the upper surface of the 2nd planarization layer and electrically connected to the common power line.
6. The LED display apparatus of claim 1, further comprising
a recessed portion provided on the 1st planarization layer for receiving the LED; and
a unit pixel having at least three pixels arranged to adjacent to one another,
wherein the recessed portion is provided at a depth different for each pixel constituting the unit pixel.
6. The LED display apparatus of claim 1, further comprising
a recessed portion provided on or in the 1st planarization layer, receiving the LED chip.
7. The LED display apparatus of claim 1, further comprising
a reflective layer disposed between the substrate and the LED.
7. The LED display apparatus of claim 1, further comprising
a reflective layer disposed between the substrate and the LED chip.
16. The LED display apparatus of claim 7,
wherein each of the 1st LED and the 2nd LED further includes:
a 1st semiconductor layer;
an active layer on the 1st semiconductor layer; and
a 2nd semiconductor layer on the active layer,
wherein a 1st pad is disposed on the 2nd semiconductor layer, and
wherein a 2nd pad is disposed on the 1st semiconductor layer.
2. The LED display apparatus of claim 1,
wherein each of the 1st and 2nd LEDs further includes:
a 1st semiconductor layer;
an active layer on the 1st semiconductor layer; and
a 2nd semiconductor layer on the active layer,
wherein the 1st pad is disposed on the 2nd semiconductor layer, and
wherein the 2nd pad is disposed on the 1st semiconductor layer.
17. The LED display apparatus of claim 16,
wherein the LED further includes
an insulating layer covering the 1st LED and the 2nd LED,
the pixel electrode is commonly connected to the 1st pad of each of the 1st LED and the 2nd LED through a 1st pad contact hole in the insulating layer, and
the common electrode is commonly connected to the 2nd pad of each of the 1st LED and the 2nd LED through a 2nd pad contact hole in the insulating layer.
3. The LED display apparatus of claim 2,
wherein the LED chip further includes
an insulating layer covering the 1st and 2nd LEDs,
the pixel electrode is commonly connected to the 1st pad of each of the 1st and 2nd LEDs through a 1st pad contact hole in the insulating layer, and
the common electrode is commonly connected to the 2nd pad of each of the 1st and 2nd LEDs through a 2nd pad contact hole in the insulating layer.
18. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 1st planarization layer, and
the common electrode is provided on the 1st planarization layer and electrically connected to the common power line.
4. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 1st planarization layer, and
the common electrode is provided on the 1st planarization layer and electrically connected to the common power line.
19. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 2nd planarization layer, and
wherein the common electrode is provided on the upper surface of the 2nd planarization layer and electrically connected to the common power line.
4. The LED display apparatus of claim 1, further comprising
a common power line provided on the substrate,
wherein
the pixel electrode is provided on an upper surface of the 1st planarization layer, and
the common electrode is provided on the 1st planarization layer and electrically connected to the common power line.
20. The LED display apparatus of claim 1, further comprising
a recessed portion provided on or in the 1st planarization layer for receiving the LED.
6. The LED display apparatus of claim 1, further comprising
a recessed portion provided on or in the 1st planarization layer, receiving the LED chip.
21. The LED display apparatus of claim 1, further comprising
a reflective layer disposed between the substrate and the LED.
7. The LED display apparatus of claim 1, further comprising
a reflective layer disposed between the substrate and the LED chip.
22. The LED display apparatus of claim 1,
wherein the LED is configured to emit a red light, a green light, a blue light, or a white light.
15. The LED display apparatus of claim 1,
wherein the LED chip is configured to emit one of a red light, a green light, a blue light, and a white light.
23. The LED display apparatus of claim 16,
wherein the 1st semiconductor layer comprises a 1st semiconductor material including an n-doped Gallium Nitride (n-GAN).
17. The LED display apparatus of claim 16,
wherein the n-GaN based semiconductor material comprises at least one of GaN, AlGaN, InGaN, AlInGaN, Si, Ge, Se, Te, and C.
24. The LED display apparatus of claim 23,
wherein the semiconductor material comprises at least one of GaN, AIGaN, InGaN, AllnGaN, Si, Ge, Se, Te, and C.
17. The LED display apparatus of claim 16,
wherein the n-GaN based semiconductor material comprises at least one of GaN, AlGaN, InGaN, AlInGaN, Si, Ge, Se, Te, and C.
25. The LED display apparatus of claim 16,
wherein the 2nd semiconductor layer comprises a 2nd semiconductor material including a p-doped GAN (p- GAN).
17. The LED display apparatus of claim 16,
wherein the n-GaN based semiconductor material comprises at least one of GaN, AlGaN, InGaN, AlInGaN, Si, Ge, Se, Te, and C.
26. The LED display apparatus of claim 25,
wherein the 2nd semiconductor material comprises one of GaN, AIGaN, InGaN, AllnGaN, Mg, Zn, and Be.
17. The LED display apparatus of claim 16,
wherein the n-GaN based semiconductor material comprises at least one of GaN, AlGaN, InGaN, AlInGaN, Si, Ge, Se, Te, and C.
27. The LED display apparatus of claim 16,
wherein the active layer includes a multi quantum well structure comprising a well layer and a barrier layer, and
wherein a band gap of the barrier layer is higher than a band gap of the well layer.
20. The LED display apparatus of claim 2,
wherein the active layer has a multi quantum well structure comprising a well layer and a barrier layer, and
wherein the barrier layer has a band gap higher than that of the well layer.
28. The LED display apparatus of claim 16,
wherein the 2nd pad is electrically isolated from the active layer and the 2nd semiconductor layer.
21. The LED display apparatus of claim 2,
wherein the 2nd pad is electrically isolated from the active layer and the 2nd semiconductor layer.
29. The LED display apparatus of claim 16,
wherein at least one of the 1st pad and the 2nd pad comprises
a conductive transparent material or a conductive reflective material.
22. The LED display apparatus of claim 1,
wherein the 1st pad and/or the 2nd pad comprises
a conductive transparent material or conductive reflective material.
30. The LED display apparatus of claim 29,
wherein the conductive transparent material comprises ITO or IZO.
29. The LED display apparatus of claim 1,
wherein at least one of the pixel electrode and the common electrode comprises ITO or IZO.
31. The LED display apparatus of claim 29,
wherein the conductive reflective material comprises one of Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, and Cr.
24. The LED display apparatus of claim 22,
wherein the conductive reflective material comprises one of Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, and Cr.
33. The LED display apparatus of claim 1,
wherein the 1st planarization layer comprises benzocyclobutene or photo acryl.
26. The LED display apparatus of claim 1,
wherein the 1st planarization layer comprises benzocyclobutene or photo acryl.
34. The LED display apparatus of claim 1,
wherein the pixel electrode overlaps with the driving TFT.
27. The LED display apparatus of claim 1,
wherein the pixel electrode overlaps with the driving TFT.
35. The LED display apparatus of claim 1,
wherein the pixel electrode is electrically connected to the driving thin film transistor through a contact hole that passes through the 1st planarization layer and the 2nd planarization layer.
28. The LED display apparatus of claim 1,
wherein the pixel electrode is electrically connected to the driving TFT through a contact hole that passes through the 1st and 2nd planarization layers.
36. The LED display apparatus of claim 1,
wherein at least one of the pixel electrode and the common electrode comprises ITO or IZO.
39. The LED display device of claim 38,
wherein the 1st electrode and the pixel electrode are made of ITO or IZO.
37. The LED display apparatus of claim 1, further comprising
a light extraction layer or a color filter layer disposed on the LED.
31. The LED display apparatus of claim 30,
wherein the light extraction layer is configured to extract light emitted from the LED chip.
38. The LED display apparatus of claim 37,
wherein the light extraction layer is configured to extract light emitted from the LED.
31. The LED display apparatus of claim 30,
wherein the light extraction layer is configured to extract light emitted from the LED chip.
39. The LED display apparatus of claim 1, further comprising
a wavelength conversion layer.
32. The LED display apparatus of claim 1, further comprising
a wavelength conversion layer.
40. The LED display apparatus of claim 18,
wherein the common power line is in parallel with a gate line.
33. The LED display apparatus of claim 4,
wherein the common power line is in parallel with a gate line.
41. The LED display apparatus of claim 20, further comprising
a unit pixel having at least three pixels arranged to adjacent to one another,
wherein the recessed portion is provided at a depth different for each pixel constituting the unit pixel.
34. The LED display apparatus of claim 6, further comprising
a unit pixel having at least three pixels arranged to adjacent to one another,
wherein the recessed portion is provided at a depth different for each of the pixels constituting the unit pixel.
42. The LED display apparatus of claim 20,
wherein a bottom surface of the LED contacts a layer different from the 1st planarization layer.
35. The LED display apparatus of claim 6,
wherein a bottom surface of the LED chip is in a direct contact with a layer different from the 1st planarization layer.
43. The LED display apparatus of claim 20,
wherein the 1st planarization layer comprises a groove formed throughout a depth direction of the 1st planarization layer, and
wherein the groove comprises the recessed portion.
36. The LED display apparatus of claim 6,
wherein the 1st planarization layer comprises a groove formed throughout a depth direction of the 1st planarization layer, and
wherein the groove comprises the recessed portion.
44. The LED display apparatus of claim 1,
wherein the LED is placed on the 1st planarization layer during a manufacturing process.
46. The LED display device of claim 45, further comprising a display area including the 1st pixel and a non-display area,
wherein the gate driving circuit is disposed in a 1st portion of the non-display area and formed by a process that is the same as a process of forming the 1st driving TFT.
Allowable Subject Matter
16. As best understood, claims 1-7 and 15-44 contain allowable subject matter. Specifically, the prior art does not disclose or make obvious “a pixel electrode provided on the 2nd planarization layer and electrically connected to the driving TFT and the 1st electrode and a common electrode provide don the 2nd planarization layer and electrically connected to the 2nd electrode” in combination with the other limitations of the claims.
Conclusion
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEANDRA M HUGHES whose telephone number is (571)272-6982. The examiner can normally be reached Generally M-Th 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached at 571-272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed:
/DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992
Conferees
/Woo H Choi/
Primary Examiner, Art Unit 3992
/Patricia L Engle/SPRS, Art Unit 3991
1 Claim 15 is not rejected on the grounds of non-statutory double patenting.
Prosecution Insights