DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 08/22/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
4. Claims 21-24, 29-33 and 35-38 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-3, 9-11 and 15-17 of Patent No. 12,073,489. Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are broader in every aspect than the patent claims and are therefore an obvious variant thereof.
5. Regarding claim 21, the application claim discloses An accelerator device comprising: a processing cluster including an array of multiprocessors coupled to an interconnect fabric; scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors; and a multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a plurality of threads, the multiprocessor including circuitry configured to: execute a first thread sub-group and a second thread sub-group, the first thread sub-group and the second thread sub-group formed based on the first thread group and respectively include a plurality of threads, the second thread sub-group has a data dependency on the first thread sub-group; and cause threads of the second thread sub-group to sleep until threads of the first thread sub-group have satisfied the data dependency. Claim 24 discloses the multiprocessor is configured to execute instructions of first thread sub-group to generate a first portion of an output data set and execute instructions of the second thread sub-group to generate a second portion of the output data set. Claim 1 of Patent No. 12,073,489 discloses An apparatus comprising: a processing cluster including an array of multiprocessors coupled to an interconnect fabric; scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors, each thread group comprising a plurality of threads and each thread comprising a plurality of instructions to be executed by at least one of the multiprocessors; and a first multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a first plurality of threads, the first multiprocessor comprising a plurality of parallel execution circuits, wherein to process the first thread group, the plurality of parallel execution circuits is to execute instructions of a first thread sub-group and instructions of a second thread sub-group, the first and second thread sub-groups formed based on the first thread group, the first and second thread sub-groups each including a plurality of threads, wherein the plurality of parallel execution circuits is to execute the instructions of the first thread sub-group to generate a first portion of an output data set and to execute the instructions of the second thread sub-group to generate a second portion of the output data set, the second thread sub-group having a data dependency on the first thread sub-group, and wherein the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency. Regarding claims 21 and 24, the only difference is that claims 21 and 24 of the instant application recite “accelerator device” and do not recite “apparatus, each thread group comprising a plurality of threads and each thread comprising a plurality of instructions to be executed by at least one of the multiprocessors; the first multiprocessor comprising a plurality of parallel execution circuits,” while claim 1 of Patent No. 12,073,489 recites. An accelerator device is
an apparatus. Regarding claims 29 and 33, claims 35 and 38, the analyses are similar to that of claims 21 and 24, the rationale of claims 21 and 24 rejection is applied in rejecting claims 29 and 33, claims 35 and 38. Therefore, the claims in the present application disclosing broader than the claims in the Patent No. 12,073,489 recite.
6. The following table shows the claims of the current application being examined and the conflicting claims of Patent No. 12,073,489.
Current Application No.
18/812,451
Patent No.
12,073,489
21+24
1
22
2
23
3
29+33
9
30+31
10
32
11
35+38
15
36
16
37
17.0
The following table shows an example of the corresponding conflicting claims of the current application and Patent No. 12,073,489.
Current Application No.
18/812,451
Claim 21+24
Patent No.
12,073,489
Claim 1
An accelerator device comprising: (claim 21)
An apparatus comprising:
a processing cluster including an array of multiprocessors coupled to an interconnect fabric; (claim 21)
a processing cluster including an array of multiprocessors coupled to an interconnect fabric;
scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors; (claim 21)
scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors,
and a multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a plurality of threads, the multiprocessor including circuitry configured to: (claim 21)
each thread group comprising a plurality of threads and each thread comprising a plurality of instructions to be executed by at least one of the multiprocessors; and a first multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a first plurality of threads, the first multiprocessor comprising a plurality of parallel execution circuits,
execute a first thread sub-group and a second thread sub-group, the first thread sub-group and the second thread sub-group formed based on the first thread group and respectively include a plurality of threads, the second thread sub-group has a data dependency on the first thread sub-group; (claim 21)
wherein to process the first thread group, the plurality of parallel execution circuits is to execute instructions of a first thread sub-group and instructions of a second thread sub-group, the first and second thread sub-groups formed based on the first thread group, the first and second thread sub-groups each including a plurality of threads, the second thread sub-group having a data dependency on the first thread sub-group,
the multiprocessor is configured to execute instructions of first thread sub-group to generate a first portion of an output data set and execute instructions of the second thread sub-group to generate a second portion of the output data set. (claim 24)
wherein the plurality of parallel execution circuits is to execute the instructions of the first thread sub-group to generate a first portion of an output data set and to execute the instructions of the second thread sub-group to generate a second portion of the output data set,
and cause threads of the second thread sub-group to sleep until threads of the first thread sub-group have satisfied the data dependency. (claim 21)
and wherein the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency.
Allowable Subject Matter
7. Claims 25-28, 34, 39 and 40 are objected to being dependent upon rejected base claims. The claims would be allowable if the base claims got allowed that including all the limitations.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michelle Chin whose telephone number is (571)270-3697. The examiner can normally be reached on Monday-Friday 8:00 AM-4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kent Chang can be reached on (571)272-7667. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300.
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/MICHELLE CHIN/
Primary Examiner, Art Unit 2614