DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kotary et al. (US 2024/0403157) and further in view of Thirumala et al. (US 2023/0236933).
Consider claim 1, Kotary et al. discloses a storage system comprising: a plurality of storage devices having non volatile memory; and two or more storage controllers, external to and operatively coupled to the plurality of storage devices, configured to: detect an addition of one or more storage memory devices comprising a compute express link (CXL), wherein the CXL is configured to provide access to the one or more storage memory devices for the two or more storage controllers, and wherein the one or more storage memory devices comprises non volatile memory and is integrated into a managed flash storage device, the managed flash storage device managed by the two or more storage controllers; store, by the two or more storage controllers, at least one of data or metadata in the one or more storage memory devices; and perform, by the two or more storage controllers, one or more storage system operations using the at least one of data or metadata (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], and [0048], Kotary et al. discloses a system with a plurality of DRAM modules and multiple controllers. The system utilizes CXL. The data stored in a DRAM module that is close to failure can be mirrored to an added DRAM module to use while the original is being replaced so as to not interrupt (or greatly reduce interruption) access to the data. Kotary et al. also discloses that non-volatile memory is in the system and that FLASH memory can be as well.).
Kotary et al. does disclose the use of FLASH based non-volatile memory, but does not specifically state that the memories used in the rejection are non-volatile FLASH memory. However being able to use non-volatile memory is well-known in the art and can easily replace the DRAM memories of Kotary et al. and deal with failures in FLASH in the same way as described for DRAM.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kotary et al. reference to use FLASH memory instead of DRAM because non-volatile memory can provide persistent data by retaining stored data with not powered therefore increased data security. The background of Thirumala et al. is used to reinforce this known benefit (Thirumala et al. [0003]).
Consider claim 2, Kotary et al. discloses the storage system of claim 1, wherein the one or more storage memory devices comprising the CXL has a same form factor as the plurality of storage devices (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], Kotary et al. discloses that the replacement DRAM can have the same vendor and configuration.).
Consider claim 3, Kotary et al. discloses the storage system of claim 1, wherein the one or more storage memory devices comprising the CXL is external to the two or more storage controllers (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], Kotary et al. discloses that the DRAM module are CXL enabled and external to controllers.).
Consider claim 4, Kotary et al. discloses the storage system of claim 1, wherein the one or more storage memory devices comprise dynamic random access memory (DRAM) (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], Kotary et al. discloses the use of DRAM).
Consider claim 5, Kotary et al. discloses the storage system of claim 1, wherein the two or more storage controllers are further configured to: transmit, via the CXL of the one or more storage memory devices, one or more communications between the two or more storage controllers (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], Kotary et al. discloses the mirroring of data over a CXL enabled system.).
Consider claim 6, Kotary et al. discloses the storage system of claim 1, wherein the two or more storage controllers are further configured to: receive an indication that the one or more storage memory devices comprising the CXL is to be removed from the storage system; and in response to receiving the indication, migrate the at least one of data or metadata from the one or more storage memory devices to one or more different locations in the storage system (abstract, Fig. 1, [0011]-[0016], [0022]-[0024], [0033], Kotary et al. discloses a system with a plurality of DRAM modules and multiple controllers. The system utilizes CXL. The data stored in a DRAM module that is close to failure can be mirrored to an added DRAM module to use while the original is being replaced and then migrates the data back once a replacement is made.).
Consider claim 7, Kotary et al. discloses the storage system of claim 1, wherein the two or more storage controllers manage one of internal error correction, encryption, or voltage level adjustments for flash memory of at least one of the plurality of storage devices and wherein the addition of the one or more storage device is non-disruptive to the storage system (abstract, Fig. 1, [0011]-[0016], [0018],[0022]-[0024], [0033], [0048], Kotary et al. discloses that error counts and voltage data is collected and managed.).
Claims 8-14 are the method claims to system claims 1-7 and are rejected in the same manner utilizing the same rationale.
Claims 15-20 are the medium claims to system claims 1-6 and are rejected in the same manner utilizing the same rationale.
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive.
The amendments have been addressed in the appropriate claim rejections above. The applicant further argues that Kotary cannot be modified to include non-volatile memory. The examiner disagrees, the invention of Kotary is related to dealing with memory failure and replacement, there does not appear to be any specific feature in Kotary that would prevent the DRAM from being replaced with FLASH.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ALSIP/Primary Examiner, Art Unit 2136