Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on December 1, 2025 has been received and entered.
Applicant’s Amendments to the Claims and Specification have been received and acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “insufficient” in claim 1 is a relative term which renders the claim indefinite. The term “insufficient” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Similar problems exist in claims 11 and 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Natu (U.S. Publication No. 2022/0179818 A1), hereafter referred to as Natu’818 in view of GARG et al. (U.S. Publication No. 2024/0095171 A1), hereafter referred to as GARG’171.
Referring to claim 1, Natu’818 as claimed, a switch, the switch (switch 203, 403, see Figs. 2, 4a, 4c) comprising: a plurality of connection interfaces (interfaces/ports such as 231, 233, 431, 433, 438, see Figs. 2, 4a, 4c), the plurality of connection interfaces being configured to connect to a plurality of processors respectively (CPU 202, Device 205, device 401, device 405, see Figs. 2, 4a,c, 5; also note: paras. [0024], [0025], and [0093]), for mutual access to a plurality of memories (memories such as memory 204, memory expander 405, 504 see paras. [0024], [0031], [0038], [0093], [0097] [0098], Figs. 2, 4a,c, 5) corresponding to the plurality of processors through the switch, the switch being configured to: receive a first memory request from a first processor of the plurality of processors, through a memory request service component corresponding to the first processor, wherein the memory request service component is within the switch, and the first memory request is sent by the first processor when a first local memory connected to the first processor is insufficient (circuitry 201 includes downstream ports 215, 217 and further coupled to the switch by a link 212 between the downstream port 215 and an upstream port 231 of the switch 203. The link 212 compatible to a first protocol, see para. [0039], Figs. 2, 4a,c, 5); convert the first memory request into a second memory request that specifies a second local memory of a second processor of the plurality of processors; and send the second memory request to a memory response service component corresponding to the second processor, wherein the memory response service component is within the switch (The switch 203 is coupled to the device 205 by a link 232 between a downstream port 233 of the switch 203 and the upstream port 251 of the device 205. The link 232 compatible to a second protocol, see paras. [0039], [0049]-[0051], Figs. 2, 4a,c, 5); convert the second memory request into a third memory request that requests to access the second local memory of the second processor; and send the third memory request to the second processor to access memory resources corresponding to the second processor (accessing memories such as memory 204, memory expander 405, 504 see paras. [0024], [0031], [0038], [0093], [0097] [0098], Figs. 2, 4a,c, 5; also note: memory circuitry including on-die memory or registers associated with the processor circuitry 502; memory circuitry 504/data storage circuitry 508, see paras. [0097]-[0099] and Fig. 5).
However, Natu’818 does not appear to teach converting the memory requests that conform to protocols of other interfaces for providing memory resources.
GARG’171 discloses converting the memory requests that conform to protocols of other interfaces for providing memory resources (allow a host application to access a memory pool outside the local rack level using normal load and store commands, use a cache coherent interface to an interface circuit for access to a different interface, see paras. [0014], [0036]; each of the memory pool servers are connected to the interface circuit via any suitable type of connection, e.g. Ethernet, Infiniband, or Fiber channel, see paras. [0049]; plurality of hosts connected to a memory pool server and share the memory resources of the memory pool server. In some embodiments, in operation, the host writes into physical address space mapped CXL-DRAM, the request is sent to the CXL root complexes, the CXL root complex generates a TLP and sends it to the interface circuit, and the interface circuit converts the TLP to remote direct memory access and sends it over the computer cluster interconnect interface, see paras. [0053] and [0054]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Natu’818’s invention to comprise converting the memory requests that conform to protocols for providing memory resources, as taught by GARG’171, in order to dynamically allocate resources through an interface circuit and shared memory pool to achieve memory disaggregation to physically separated memory resources avoiding limitations of some memory interface links (see para. [0036]).
As to claim 2, Natu’818 also discloses the plurality of connection interfaces are configured to operate according to a cache-coherent interconnect protocol (CXL, see paras. [0040], [0049], [0053], [0055], [0057]-[0059]); and wherein the plurality of processors are interconnected with the switch via an I/O sub-protocol of the cache-coherent interconnect protocol (CXL.IO, see para. [0060]).
As to claim 3, Natu’818 also discloses the switch is configured to: receive the first memory request from the first processor based a memory sub-protocol of the cache-coherent interconnect protocol through the memory request service component; and send the third memory request to the second processor based on a cache sub-protocol of the cache-coherent interconnect protocol through the memory response service component (CXL mem, see Figs. 4b,c and paras. [0019], 0040], [0049], [0053], [0055], [0057]-[0060], [0062]).
As to claim 4, Natu’818 also discloses the plurality of processors each have a corresponding pair of memory request service component and memory response service component; wherein the memory request service component is configured to process memory requests from the corresponding processor, and the memory response service component is configured to respond to the memory requests to provide memory resources to the processor that sent the memory requests (circuitry 201 includes downstream ports 215, 217 and further coupled to the switch by a link 212 between the downstream port 215 and an upstream port 231 of the switch 203. The link 212 compatible to a first protocol. The switch 203 is coupled to the device 205 by a link 232 between a downstream port 233 of the switch 203 and the upstream port 251 of the device 205. The link 232 compatible to a second protocol, see paras. [0039], [0049]-[0051], Figs. 2, 4a,c, 5).
As to claim 5, Natu’818 also discloses the pair of memory request service component and memory response service component is a Consumer-Provider component pair (circuitry 201 includes downstream ports 215, 217 and further coupled to the switch by a link 212 between the downstream port 215 and an upstream port 231 of the switch 203. The link 212 compatible to a first protocol. The switch 203 is coupled to the device 205 by a link 232 between a downstream port 233 of the switch 203 and the upstream port 251 of the device 205. The link 232 compatible to a second protocol, see paras. [0039], [0049]-[0051], Figs. 2, 4a,c, 5; also note: consumer, see paras. [0013], [0032] and produce, see para. [0014]).
As to claim 6, Natu’818 also discloses the plurality of pairs of memory request service component and memory response service component are interconnected through a crossbar switch matrix (switch 203, 403, see Figs. 2, 4a, 4c and paras. [0014]-[0019], [0049], [0055]).
As to claim 7, Natu’818 also discloses each of the memory request service components further comprises an interface for connecting an accelerator (accelerator, see Fig. 4b, 5, paras. [0036], [0092], [0093], [0095], [0101], ]0110]).
As to claim 8, Natu’818 also discloses the accelerator is an accelerator for near-memory computing (accelerator, see Fig. 4b, 5, paras. [0036], [0092], [0093], [0095], [0101], ]0110]; also note: CXL, see Figs. 4b,c and paras. [0019], 0040], [0049], [0053], [0055], [0057]-[0060], [0062]).
As to claim 9, Natu’818 also discloses the switch, based on address information of the memory resources of the second processor to be accessed, converts the first memory request into a second memory request carrying the address information and conforming to a bus protocol of the switch, and sends the second memory request to the memory response service component corresponding to the second processor through the bus within the switch (circuitry 201 includes downstream ports 215, 217 and further coupled to the switch by a link 212 between the downstream port 215 and an upstream port 231 of the switch 203. The link 212 compatible to a first protocol. The switch 203 is coupled to the device 205 by a link 232 between a downstream port 233 of the switch 203 and the upstream port 251 of the device 205. The link 232 compatible to a second protocol, see paras. [0039], [0049]-[0051], Figs. 2, 3, 4a,c, 5; address decode isolation to facilitate the communication between a downstream port of the root complex and an upstream port of a device through a switch, see paras. [0053], [0060], [0061]).
As to claim 10, Natu’818 also discloses the switch, based on the address information of the memory resources of the second processor to be accessed, remaps original memory address information carried in the first memory request to the address information of the memory resources, and converts the remapped first memory request into the second memory request conforming to the bus protocol of the switch (address decode isolation to facilitate the communication between a downstream port of the root complex and an upstream port of a device through a switch, see paras. [0053], [0060]-[0063] and Fig. 4c; also note: communication from first protocol to second protocol, see paras. [0016]-[0018], [0039], [0046]).
Note claims 11 and 15 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 12 and 17 recite similar limitations of claim 3. Therefore they are rejected based on the same reason accordingly.
Note claim 13 recites similar limitations of claim 4. Therefore it is rejected based on the same reason accordingly.
Note claims 14 and 18 recite similar limitations of claim 6. Therefore they are rejected based on the same reason accordingly.
Note claim 16 recites similar limitations of claim 2. Therefore it is rejected based on the same reason accordingly.
Note claim 19 recites similar limitations of claim 7. Therefore it is rejected based on the same reason accordingly.
Note claim 20 recites similar limitations of claim 8. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 12/1/2025 have been fully considered but they are moot due to new grounds of rejection.
In summary, Natu’818 and GARG’171 teach the claimed limitations as set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181