DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Please Note: Examiner alerted Mr. Newton (Reg. No. 73,157) to the statutory double patenting issue prior to this office action. Mr. Newton indicated to Examiner that he would review Claim 19 but did not respond back to Examiner with a decision.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 19, 20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 19, 20 of prior U.S. Patent No. 12101069. This is a statutory double patenting rejection.
Please Note: The claims of Patent 12101069 are bolded and in parenthesis.
Regarding Claim 19, A variable gain amplifier comprising: a first resistor ladder comprising resistor legs coupled to first resistors and second resistors, wherein each resistor leg comprises one or more resistors (A variable gain amplifier comprising: a first resistor ladder comprising resistor legs coupled to first resistors and second resistors, wherein each resistor leg comprises one or more resistors); a second resistor ladder comprising additional resistor legs coupled to third resistors and fourth resistors, wherein each resistor leg comprises one or more additional resistors (a second resistor ladder comprising additional resistor legs coupled to third resistors and fourth resistors, wherein each resistor leg comprises one or more additional resistors); a first circuit segment comprising: a first plurality of differential switches comprising first differential switches connected to the first resistor ladder and second differential switches connected to a first output nodes, wherein a transistor in each of the first differential switches is coupled to a first electrical line that interconnects the first resistors (a first circuit segment comprising: a first plurality of differential switches comprising first differential switches connected to the first resistor ladder and second differential switches connected to a first output nodes, wherein a transistor in each of the first differential switches is coupled to a first electrical line that interconnects the first resistors), and wherein a different transistor in each of the first differential switches is coupled to a second electrical line that interconnects the second resistors (and wherein a different transistor in each of the first differential switches is coupled to a second electrical line that interconnects the second resistors); and a second plurality of differential switches comprising third differential switches connected to the first resistor ladder and fourth differential switches connected to the first output nodes (and a second plurality of differential switches comprising third differential switches connected to the first resistor ladder and fourth differential switches connected to the first output nodes), wherein a transistor in each of the third differential switches is coupled to the first electrical line and a different transistor in each of the fourth differential switches is coupled to the second electrical line (wherein a transistor in each of the third differential switches is coupled to the first electrical line and a different transistor in each of the fourth differential switches is coupled to the second electrical line); and a second circuit segment comprising: a third plurality of differential switches comprising fifth differential switches connected to the second resistor ladder and sixth differential switches connected to second output nodes (and a second circuit segment comprising: a third plurality of differential switches comprising fifth differential switches connected to the second resistor ladder and sixth differential switches connected to second output nodes), wherein a transistor in each of the fifth differential switches is coupled to a third electrical line that interconnects the third resistors and a different transistor in each of the sixth differential switches is coupled to a fourth electrical line that interconnects the fourth resistors (wherein a transistor in each of the fifth differential switches is coupled to a third electrical line that interconnects the third resistors and a different transistor in each of the sixth differential switches is coupled to a fourth electrical line that interconnects the fourth resistors); and a fourth plurality of differential switches comprising seventh differential switches connected to the second resistor ladder and eighth differential switches connected to the second output nodes (and a fourth plurality of differential switches comprising seventh differential switches connected to the second resistor ladder and eighth differential switches connected to the second output nodes), wherein a transistor in each of the seventh differential switches is coupled to the third electrical line and a different transistor in each of the eighth differential switches is coupled to the fourth electrical line (wherein a transistor in each of the seventh differential switches is coupled to the third electrical line and a different transistor in each of the eighth differential switches is coupled to the fourth electrical line).
Regarding Claim 20, The variable gain amplifier of claim 19, further comprising an additional transistor connected to the first circuit segment and a different additional transistor connected to the second circuit segment (The variable gain amplifier of claim 19, further comprising an additional transistor connected to the first circuit segment and a different additional transistor connected to the second circuit segment), wherein the additional transistor is configured to receive a first input signal corresponding to a differential signal pair (wherein the additional transistor is configured to receive a first input signal corresponding to a differential signal pair) and the different additional transistor is configured to receive a second input signal corresponding to the differential signal pair (and the different additional transistor is configured to receive a second input signal corresponding to the differential signal pair).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Park et al. (US 2020/0144978) Figure 2, Section 0047 teaches a variable gain amplifier (VGA) comprising transistors, Rogers et al. (US 2006/0164164) Figure 2, Section 0014 teaches a VGA comprising transistors, Broekuert (US 2021/0021246) Figure 1, Section 0030 teaches a VGA comprising differential transistor pairs, Forey et al. (US 2019/0207576) Figure 3, Sections 0039, 0040 teaches a VGA comprising transistors and resistors, Gorecki (US 2018/0287577) Figure 3, Section 0046 teaches a VGA comprising transistors and resistors, and Giridharan (US 9,564,863) teaches a VGA comprising differential transistor pairs and a plurality of resistors. The prior art of record, however fails to teach or render obvious the following features:
Regarding Claim 1, a first set of differential switches connected to the resistor ladder network, wherein each respective differential switch of the first set of differential switches is coupled differentially to a first electrical line that interconnects the first plurality of resistors, and a second electrical line that interconnects the second plurality of resistors; a second set of differential switches connected to a set of output nodes, wherein the set of output nodes is coupled to the resistor ladder network; a third set of differential switches connected to the resistor ladder network, wherein each respective differential switch of the third set of differential switches is coupled differentially to the first electrical line and the second electrical line; a fourth set of differential switches connected to the set of output nodes; and a fifth transistor and a sixth transistor comprising a differential pair coupled to a differential input signal, wherein the fifth transistor is connected to the first set of differential switches and the sixth transistor connected to the third set of differential switches. All claims that depend from Claim 1 are allowable for the same reasons set forth above.
Regarding Claim 9, a first set of differential switches connected to the resistor ladder network, wherein each respective differential switch of the first set of differential switches is coupled differentially to a first electrical line that interconnects the first plurality of resistors, and a second electrical line that interconnects the second plurality of resistors; a second set of differential switches connected to a set of output nodes, wherein the set of output nodes is coupled to the resistor ladder network; a third set of differential switches connected to the resistor ladder network, wherein each respective differential switch of the third set of differential switches is coupled differentially to the first electrical line and the second electrical line; a fourth set of differential switches connected to the set of output nodes; and a fifth transistor and a sixth transistor comprising a differential pair coupled to a differential input signal, wherein the fifth transistor is connected to the first set of differential switches and the sixth transistor connected to the third set of differential switches. All claims that depend from Claim 9 are allowable for the same reasons set forth above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Katayama et al. (US 2015/0163015) Figure 9, Section 0019 teaches a DC offset compensator and Roeckner et al. (US 2019/0372538) Section 0047 teaches use of binary-weighted currents both of which are disclosed in Applicants’ specification but not claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYMOND S DEAN whose telephone number is (571)272-7877. The examiner can normally be reached Monday-Friday, 6:00-2:30, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Anthony S Addy can be reached at 571-272-7795. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RAYMOND S DEAN/ Primary Examiner, Art Unit 2645 Raymond S. Dean
August 18, 2026
Prosecution Insights