DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5-14, 16-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hassan (Pub. No.: US 2016/0241211 A1) and further in view of MYOUNG (Pub. No.: US 2022/0216856 A1).
With respect to claim 1:
Hassan discloses an amplifier comprising: a first input transistor coupled to a first output node (fig. 3, item Q1 represent the first input transistor coupled to node N1); a second input transistor coupled to a second output node (fig. 3, item Q2 represent the second input transistor coupled to node N2); and a common mode impedance tuning circuit coupled between the first output node and the second output node (fig. 3, item 350 is a common mode impedance tuning circuit), wherein the common mode impedance tuning circuit is configured to: provide a modulation response when the amplifier is operating in a first mode (fig. 4, parag. 0031-0034); and provide a second modulation response, different than the first response, when the amplifier is operating in a second mode (fig. 5, parag. 0035-0037);
Hassan discloses modulation but not explicitly disclose amplitude modulation;
MYOUNG discloses amplitude modulation (parag. 0030). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of MYOUNG into the teaching of Hassan for suppression of carrier frequency harmonics that can be integrated into a semiconductor die.
With respect to claims 2, 14:
MYOUNG discloses the amplifier of claim 1, wherein: during the first mode, the amplifier is configured to process radio-frequency signals using a first set of wireless modulation schemes; and during the second mode, the amplifier is configured to process radio-frequency signals using a second set of wireless modulation schemes different than the first set of wireless modulation schemes (parag. 0030).
With respect to claims 5, 16:
Hassan discloses the amplifier of claim 1, wherein the common mode impedance tuning circuit comprises a switch coupled to a virtual ground node in the amplifier, and wherein the switch is selectively deactivated in the first mode and is selectively activated in the second mode (fig. 3, para. 0033, 0040).
With respect to claims 6, 17:
Hassan discloses the amplifier of claim 5, wherein the common mode impedance tuning circuit further comprises: a first impedance tuning component coupled between the first output node and the virtual ground node; and a second impedance tuning component coupled between the second output node and the virtual ground node (fig. 3 with 302 coupled between N1 and N3. Also, 303 coupled between N2 and N3).
With respect to claims 7, 18:
Hassan discloses the amplifier of claim 6, wherein: the first impedance tuning component comprises a first fixed or adjustable capacitor; and the second impedance tuning component comprises a second fixed or adjustable capacitor (fig. 4, items 302 and 303 are adjustable capacitors).
With respect to claim 8:
MYOUNG discloses the amplifier of claim 5, wherein when the switch is deactivated in the first mode, the first AMAM response exhibits peaking (parag. 0029).
With respect to claim 9:
MYOUNG discloses the amplifier of claim 8, wherein when the switch is activated in the second mode, the second AMAM response exhibits less peaking or a flatter response relative to the first AMAM response (0029).
With respect to claim 10:
MYOUNG discloses the amplifier of claim 1, wherein the common mode impedance tuning circuit is further configured to: provide a first amplitude modulation to phase modulation (AMPM) response when the amplifier is operating in the first mode, and provide a second amplitude modulation to phase modulation (AMPM) response, different than the first AMPM response, when the amplifier is operating in the second mode (parag. 0030 discloses amplifier response in different mode one of which is amplitude-phase modulation).
With respect to claim 11:
MYOUNG discloses the amplifier of claim 10, wherein during the first mode, the first AMPM response exhibits peaking (parag. 0029).
With respect to claim 12:
MYOUNG discloses the amplifier of claim 11, wherein during the second mode, the second AMPM response exhibits less peaking or a flatter response relative to the first AMPM response (parag. 0029).
With respect to claim 13:
Hassan discloses an amplifier comprising: a first input transistor coupled to a first output node (fig. 3, item Q1 represent the first input transistor coupled to node N1); a second input transistor coupled to a second output node (fig. 3, item Q2 represent the second input transistor coupled to node N2); and a common mode impedance tuning circuit coupled between the first output node and the second output node (fig. 3, item 350 is a common mode impedance tuning circuit), wherein the common mode impedance tuning circuit is configured to: provide a first amplitude modulation response when the amplifier is operating in a first mode (fig. 4, parag. 0031-0034); and provide a second modulation response, different than the first AMPM response, when the amplifier is operating in a second mode (fig. 5, parag. 0035-0037);
Hassan discloses modulation but not explicitly disclose amplitude/phase modulation;
MYOUNG discloses amplitude to phase modulation mode (parag. 0030). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of MYOUNG into the teaching of Hassan for suppression of carrier frequency harmonics that can be integrated into a semiconductor die.
With respect to claim 20:
Hassan discloses an amplifier comprising: a first input transistor coupled to a first output node (fig. 3, item Q1 represent the first input transistor coupled to node N1); a second input transistor coupled to a second output node fig. 3, item Q2 represent the second input transistor coupled to node N2); and a common mode impedance tuning circuit coupled between the first output node and the second output node (fig. 3, item 350 is a common mode impedance tuning circuit);
Hassan does not explicitly disclose wherein the common mode impedance tuning circuit is configured to: provide a first non-linear distortion response when the amplifier is operating under a first condition; and provide a second non-linear distortion response, different than the first non-linear response, when the amplifier is operating under a second condition different than the first condition.
MYOUNG discloses a first non-linear distortion response when the amplifier is operating under a first condition; and provide a second non-linear distortion response, different than the first non-linear response, when the amplifier is operating under a second condition different than the first condition (parag. 0030); It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of MYOUNG into the teaching of Hassan for suppression of carrier frequency harmonics that can be integrated into a semiconductor die.
Claims 3, 4, 15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hassan (Pub. No.: US 2016/0241211 A1), MYOUNG (Pub. No.: US 2022/0216856 A1) as applied to claim 1 above and further in view of Sako (Pub. No.: US 2011/0038429 A1).
With respect to claim 3:
The rejection of claim 1 is incorporated; Hassan and MYOUNG do not explicitly disclose wherein the first set of wireless modulation schemes comprises one or more of quadrature phase shift keying (QPSK), binary phase shift keying (BPSK), and 8-quadrature amplitude modulation (8-QAM).
Sako discloses wireless modulation having quadrature phase shift keying (QPSK) (parag. 0454).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Sako into the teaching of Hassan in view of MYOUNG in order to provide good linearity and high efficiency.
With respect to claims 4, 15:
Sako discloses the amplifier of claim 3, wherein the second set of wireless modulation schemes comprises one or more of: 64-quadature amplitude modulation (64-QAM), 128-quadrature amplitude modulation (128-QAM), 256-quadrature amplitude modulation (256-QAM), 512-quadrature amplitude modulation (512-QAM), and 1024-quadrature amplitude modulation (1024-QAM) (parag. 0454 discloses 64-QAM).
With respect to claim 19:
MYOUNG discloses the amplifier of claim 16, wherein: when the switch is deactivated in the first mode, the first AMPM response exhibits some peaking; and when the switch is activated in the second mode, the second AMPM response exhibits less peaking or a flatter response relative to the first AMPM response (0029).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJIBOLA A AKINYEMI whose telephone number is (571)270-1846. The examiner can normally be reached Monday-Friday 8:00am-5:00pm, EST.
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/AJIBOLA A AKINYEMI/Primary Examiner, Art Unit 2649
