DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements filed on 11/18/2024 and 12/18/2024 have been acknowledged and considered by examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments for the rejection of claims under 35 U.S.C. § 103 have been fully considered but are moot because the new ground of rejection does not rely on any reference(s) applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 18 and 20 are objected to because of the following informalities: Both claims recite “of the at least one lower-level ASICs” (claim 18, line 2 and claim 20, line 3, respectively. However, independent claim 1 establishes antecedent basis in the singular as “at least one lower-level ASIC” (line 5). Appropriate correction is required to change “ASICs” to “ASIC” to maintain proper antecedent basis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 6 and 9:
Claim 6 recites the limitation “the self- test function” (lines 2-3 and claim 9, line 4, respectively). However, a self-test function is not established in claim 1 as it is first established in claim 2. The claim is indefinite because it is unclear whether a new antecedent basis should be established in claim 6, or if claim 6 should be amended to depend on claim 2. For the purpose of examination and the prior art rejections below, the claim is interpreted as being dependent on claim 1 with an antecedent basis established for “the self-test function”.
Claim 9 recites the limitation “the self- test function” (line 4). However, a self-test function is not established in claim 8. The claim is indefinite because it is unclear whether a new antecedent basis should be established in claim 9, or if claim 9 is missing a limitation establishing the self-test function. For the purpose of examination and the prior art rejections below, the claim is interpreted as being dependent on claim 8 with an antecedent basis established for “the self-test function”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 13-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Oustry et al. (hereinafter, “Oustry”, US 2024/0369986) in view of Buecher et al. (US 2015/0160045).
With regards to claim 1 and 8, Oustry teaches a circuit arrangement with a diagnostic function for use in position-measuring devices (control system for a rotary position sensor assessing signal integrity; [0003]-[0005]), the circuit arrangement comprising:
a higher-level application-specific integrated circuit (ASIC) (motor controller 504) having a diagnostic unit (sensor signal processing module 528) and an electronic circuit configured (the motor control module 530) to perform a first intended function (motor controller 504 implemented as an ASIC processor having a sensor signal processing module 528 and a motor control module 530 performing the intended function of closed-loop motor control; [0059], [0073], [0125], [0140]); and
at least one lower-level unit having a parameter-measuring unit and an electronic circuit configured to perform a second intended function (resolver 200 is the position sensor which transmits sine and cosine feedback signals; [0046], [0051]-[0054]),
wherein the parameter-measuring unit and the diagnostic unit are interconnected via a data channel (the communication wiring passing the signals back to the motor controller; [0063]),
wherein the parameter-measuring unit is configured to determine a plurality of functional parameters of the electronic circuit of the lower-level ASIC, and to transmit the functional parameters via the data channel to the diagnostic unit (the resolver 200 generates and transmits raw analog sine and cosine feedback signal amplitudes to the motor controller; [0051], [0054]), and
wherein the diagnostic unit is configured to establish operational readiness of the electronic circuit of the at least one lower-level ASIC by evaluating the functional parameters (the motor controller 504 establishes functional safety and reliability by performing signal integrity checks on raw parameters, evaluating whether the maximum/minimum amplitudes and the sum of their squares remain within the allowed limits before permitting normal operation; [0125]-[0139]).
Oustry does not teach the lower-level unit being implemented as an ASIC.
However, Buecher teaches the lower-level unit being implemented as an ASIC (the measurement-value detecting functional units are implemented as separate components designed as ASICs; [0011]-[0012], [0027]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the lower-level unit of Oustry to incorporate the teachings of Buecher wherein the lower-level unit being implemented as an ASIC to allow for a higher level of integration which allows for a better solution in terms of cost and space ([0008], [0035] Buecher).
With regards to claim 6, (For the purpose of examination, claim 6 is interpreted as being dependent on claim 1 with an antecedent basis established for “the self-test function”.) Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry further teaches wherein the diagnostic unit includes a diagnostic controller configured to control the sequence of the self- test function (the motor controller includes processor 2302 configured to execute instructions to perform the signal integrity checks; [0153]), an interface unit configured to communicate with the parameter-measuring unit via the data channel (the input interfaces 516/520 receiving feedback signals; [0064]-[0066]), and a device interface configured to communicate with subsequent electronics via an external data channel (the communication interface 2306 configured to communicate with external networks such as a CAN network; [0156]).
With regards to claim 7, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry further teaches wherein the diagnostic unit includes a memory configured to store the functional parameters and/or threshold values for the evaluation of the functional parameters and/or further rules for the evaluation of the functional parameters (the motor controller includes memory 2304 storing the data and threshold limit values utilized during the evaluation; [0112], [0130], [0154]-[0155]).
With regards to claim 13, Oustry as modified teaches the circuit arrangement as recited in claim 8. Oustry further teaches wherein the diagnostic unit includes a diagnostic controller (processor 2302), an interface unit (input interfaces 516/520), and a device interface (communication interface 2306), the method further comprising: the diagnostic controller controlling a sequence of a self-test function (the motor controller includes processor 2302 configured to execute instructions to perform the signal integrity checks; [0153]), communication being performed through the interface unit with the parameter- measuring unit via the data channel (the input interfaces 516/520 receiving feedback signals; [0064]-[0066]), and communication being performed through the device interface with subsequent electronics via an external data channel (the communication interface 2306 configured to communicate with external networks such as a CAN network; [0156]).
With regards to claim 14, Oustry as modified teaches the circuit arrangement as recited in claim 8. Oustry further teaches wherein the diagnostic unit includes a memory in which are stored the functional parameters and/or threshold values for the evaluation of the functional parameters and/or further rules for the evaluation of the functional parameters (the motor controller includes memory 2304 storing the data and threshold limit values utilized during the evaluation; [0112], [0130], [0154]-[0155]).
With regards to claim 15, Oustry as modified teaches a position-measuring device comprising the circuit arrangement according to claim 1 (rotary position sensor; [0003] Oustry).
With regards to claim 16, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry further teaches wherein the functional parameters are diagnostic parameters distinct from outputs generated in performing the first intended function and the second intended function (the raw minimum/maximum amplitude limits and sum of squares used for the signal integrity checks are diagnostic parameters distinct from the actual rotational speed and direction outputs generated to control the motor; [0056], [0125]-[0139]).
With regards to claim 17, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry further teaches wherein the at least one lower-level ASIC is not configured to establish operational readiness of the electronic circuit of the at least one lower-level ASIC (the resolver 200 simply generates raw analog sine and cosine feedback signals and contains no internal diagnostic evaluation logic; [0051], [0125]-[0139]).
With regards to claim 20, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry further teaches wherein the functional parameters include at least one of voltage values at defined measurement points of the electronic circuit of a respective lower-level ASIC of the at least one lower-level ASICs, current drawn by subcircuits and/or by the electronic circuit of the respective lower-level ASIC, resistance values, characteristics of a digital signal, and/or processing times of subcircuits of the electronic circuit of the respective lower-level ASIC (the functional parameters evaluated during the integrity checks include the maximum and minimum amplitude values of the signals and the sum of the squares of the signals; [0130]-[0139]).
Claims 2, 5, 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Oustry et al. (hereinafter, “Oustry”, US 2024/0369986) in view of Buecher et al. (US 2015/0160045) and further in view of Morici et al. (hereinafter, “Morici”; US 2016/0103173).
With regards to claims 2, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry as modified does not teach wherein the parameter-measuring unit includes a sequence controller configured to control a sequence of a self-test function, measurement means configured to determine the functional parameters through measurement at at least one measurement point of the electronic circuit, and an interface unit configured to communicate with the higher-level ASIC via the data channel.
However, Morici teaches wherein the parameter-measuring unit includes a sequence controller configured to control a sequence of a self-test function (test circuit 360 that controls and initiates the execution of the basic functionality test; [0053], [0056]), measurement means configured to determine the functional parameters through measurement at at least one measurement point of the electronic circuit (analyzing output test data using ADC 310 and a multiplexer 312 connected to specific measurement points within the signal path; [0038], [0053], [0057]), and an interface unit configured to communicate with the higher-level ASIC via the data channel (input/output interface circuit 340 configured to transmit parameters to an external receiver/control unit; [0049], [0055]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Morici wherein the parameter-measuring unit includes a sequence controller configured to control a sequence of a self-test function, measurement means configured to determine the functional parameters through measurement at at least one measurement point of the electronic circuit, and an interface unit configured to communicate with the higher-level ASIC via the data channel to increase the reliability and the availability of the electronic devices and to achieve higher safety metrics ([0003], [0006], [0026] Morici).
With regards to claim 5, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry as modified does not teach wherein the parameter-measuring unit includes at least one signal generator configured to generate at least one electrical signal and feed the at least one electrical signal to at least one feed point of the electronic circuit.
However, Morici teaches wherein the parameter-measuring unit includes at least one signal generator configured to generate at least one electrical signal and feed the at least one electrical signal to at least one feed point of the electronic circuit (the test circuit 360 acts as a signal generator providing an electrical signal and feeds it via the multiplexer 312 to the first amplitude offset correction circuit 314; [0038], [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Morici wherein the parameter-measuring unit includes at least one signal generator configured to generate at least one electrical signal and feed the at least one electrical signal to at least one feed point of the electronic circuit to increase the reliability and the availability of the electronic devices and to achieve higher safety metrics ([0003], [0006], [0026] Morici).
With regards to claim 9, (For the purpose of examination, claim 9 is interpreted as being dependent on claim 8 with an antecedent basis established for “the self-test function”.) Oustry as modified teaches the method as recited in claim 8. Oustry as modified does not teach wherein the parameter-measuring unit includes a sequence controller, measurement means, and an interface unit, the method further comprising: the sequence controller controlling a sequence of the self-test function, the measurement means determining the functional parameters through measurement at at least one measurement point of the electronic circuit, and communication being performed through the interface unit with the higher-level ASIC via the data channel.
However, Morici teaches wherein the parameter-measuring unit includes a sequence controller (test circuit 360), measurement means (ADC 310), and an interface unit (input/output interface circuit 340), the method further comprising: the sequence controller controlling a sequence of the self-test function (test circuit 360 that controls and initiates the execution of the basic functionality test; [0053], [0056]), the measurement means determining the functional parameters through measurement at at least one measurement point of the electronic circuit (analyzing output test data using ADC 310 and a multiplexer 312 connected to specific measurement points within the signal path; [0038], [0053], [0057]), and communication being performed through the interface unit with the higher-level ASIC via the data channel (input/output interface circuit 340 configured to transmit parameters to an external receiver/control unit; [0049], [0055]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Morici wherein the parameter-measuring unit includes a sequence controller, measurement means, and an interface unit, the method further comprising: the sequence controller controlling a sequence of the self-test function, the measurement means determining the functional parameters through measurement at at least one measurement point of the electronic circuit, and communication being performed through the interface unit with the higher-level ASIC via the data channel to increase the reliability and the availability of the electronic devices and to achieve higher safety metrics ([0003], [0006], [0026] Morici).
With regards to claim 12, Oustry as modified teaches the method as recited in claim 8. Oustry as modified does not teach wherein the parameter-measuring unit includes at least one signal generator that generates at least one electrical signal and feeds it to at least one feed point of the electronic circuit.
However, Morici teaches wherein the parameter-measuring unit includes at least one signal generator that generates at least one electrical signal and feeds it to at least one feed point of the electronic circuit (the test circuit 360 acts as a signal generator providing an electrical signal and feeds it via the multiplexer 312 to the first amplitude offset correction circuit 314; [0038], [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Morici wherein the parameter-measuring unit includes at least one signal generator that generates at least one electrical signal and feeds it to at least one feed point of the electronic circuit to increase the reliability and the availability of the electronic devices and to achieve higher safety metrics ([0003], [0006], [0026] Morici).
Claims 3, 4, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Oustry et al. (hereinafter, “Oustry”, US 2024/0369986) in view of Buecher et al. (US 2015/0160045) and further in view of Jang et al. (hereinafter, “Jang”; KR 101826779).
With regards to claim 3, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry as modified does not teach wherein the parameter-measuring unit includes a memory configured to store the functional parameters.
However, Jang teaches wherein the parameter-measuring unit includes a memory configured to store the functional parameters (a slave internal sensor 130 includes a diagnostic register 132 configured to store diagnostic data; [0038], [0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Jang wherein the parameter-measuring unit includes a memory configured to store the functional parameters to accurately test critical thresholds and directly trigger external safety warnings ([0005], [0051] Jang).
With regards to claim 4, Oustry as modified teaches the circuit arrangement as recited in claim 3. Jang further teaches wherein the memory is configured to be written to and/or erased by the diagnostic unit (diagnostic register 132 stores diagnostic data received from the microcontroller unit 100 requiring the master to write to and overwrite the memory for subsequent diagnostic test cycles ([0029], [0039], [0043]).
With regards to claim 10, Oustry as modified teaches the method as recited in claim 8. Oustry as modified does not teach wherein the parameter-measuring unit includes a memory in which the functional parameters are stored.
However, Jang teaches wherein the parameter-measuring unit includes a memory in which the functional parameters are stored (a slave internal sensor 130 includes a diagnostic register 132 configured to store diagnostic data; [0038], [0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of Jang wherein the parameter-measuring unit includes a memory in which the functional parameters are stored to accurately test critical thresholds and directly trigger external safety warnings ([0005], [0051] Jang).
With regards to claim 11, Oustry as modified teaches the circuit arrangement as recited in claim 3. Jang further teaches wherein the memory is written to and/or erased by the diagnostic unit (diagnostic register 132 stores diagnostic data received from the microcontroller unit 100 requiring the master to write to and overwrite the memory for subsequent diagnostic test cycles ([0029], [0039], [0043]).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Oustry et al. (hereinafter, “Oustry”, US 2024/0369986) in view of Buecher et al. (US 2015/0160045) and further in view of Applicant Admitted Prior Art (AAPA).
With regards to claim 18, Oustry as modified teaches the circuit arrangement as recited in claim 1. Oustry as modified does not teach wherein each lower-level ASIC of the at least one lower-level ASICs is arranged within a respective position sensor, and wherein the higher-level ASIC is arranged within a further position sensor.
However, Applicant Admitted Prior Art (AAPA) of the instant specification admits that it is known in the art to provide a position-measuring device (rotary encoder) comprising a single-turn scanning unit including an ASIC, and a plurality of multi-turn scanning units each including an ASIC ([0004]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC architecture of Oustry as modified to incorporate the teachings of the AAPA wherein each lower-level ASIC of the at least one lower-level ASICs is arranged within a respective position sensor, and wherein the higher-level ASIC is arranged within a further position sensor to organize the encoder’s architecture to its known mechanical and functional stages.
With regards to claim 19, Oustry as modified teaches the circuit arrangement as recited in claim 18. AAPA further teaches wherein each position sensor is a multi-turn position sensor and wherein the further position sensor is a single-turn position sensor (a position-measuring device (rotary encoder) comprising a single-turn scanning unit including an ASIC, and a plurality of multi-turn scanning units each including an ASIC ([0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSAMAH MURSHED whose telephone number is (571)272-9534. The examiner can normally be reached Monday - Friday, 11 a.m. 8 p.m. ET..
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/OSAMAH MURSHED/ Examiner, Art Unit 2858
/STEVEN L YENINAS/ Primary Examiner, Art Unit 2858
