Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 14, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, and similarly claim 14, 20, is rejected on the basis that it contains an improper Markush grouping of alternatives. See In re Harnisch, 631 F.2d 716, 721-22 (CCPA 1980) and Ex parte Hozumi, 3 USPQ2d 1059, 1060 (Bd. Pat. App. & Int. 1984). A Markush grouping is proper if the alternatives defined by the Markush group (i.e., alternatives from which a selection is to be made in the context of a combination or process, or alternative chemical compounds as a whole) share a “single structural similarity” and a common use. A Markush grouping meets these requirements in two situations. First, a Markush grouping is proper if the alternatives are all members of the same recognized physical or chemical class or the same art-recognized class, and are disclosed in the specification or known in the art to be functionally equivalent and have a common use. Second, where a Markush grouping describes alternative chemical compounds, whether by words or chemical formulas, and the alternatives do not belong to a recognized class as set forth above, the members of the Markush grouping may be considered to share a “single structural similarity” and common use where the alternatives share both a substantial structural feature and a common use that flows from the substantial structural feature. See MPEP § 2117.
The Markush grouping of claim 9, and similarly claim 14, 20, is improper because the alternatives defined by the Markush grouping do not share both a single structural similarity and a common use for the following reasons: the operations of the group are not functionally equivalent.
To overcome this rejection, Applicant may set forth each alternative (or grouping of patentably indistinct alternatives) within an improper Markush grouping in a series of independent or dependent claims and/or present convincing arguments that the group members recited in the alternative within a single claim in fact share a single structural similarity as well as a common use.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7, 10-12, 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sassone et al., US Patent Application Publication 2013/0185516 (hereinafter Sassone) in view of Gara et al., US Patent Application Publication 2009/0006762 (hereinafter Gara).
Regarding claim 1, Sassone teaches:
A device comprising: a processor core (see e.g. fig. 1 processor); a memory configured to store a set of data that includes a data element (see e.g. para. [0030], a level of memory in the hierarchy above the lowest level cache; the memory stores data for a loop including a last data element of the loop); and a circuit coupled between the processor core and the cache memory (see e.g. fig. 1, para. [0032], hardware prefetcher acts between the processor and memory to prefetch information for the processor once a loop instruction is encountered in the processor), wherein the processor core is configured to: cause the circuit to retrieve a subset of the set of data that includes the data element (see e.g. para. [0031-2], the loop instruction causes data to be retrieved for a loop that includes a last data element retrieved for the loop); retrieve the data element from the circuit (see e.g. para. [0031-4], the processor executes a loop by fetching one or more instructions and/or data including a last data element that is retrieved); and specify an amount of the set of data to fetch ahead of the processor core retrieving the data element (see e.g. para. [0031-4], a loop instruction specifies an amount of data to prefetch through specifying the max loop count; data are prefetched ahead of the last data element being retrieved).
Sassone fails to explicitly teach wherein the memory at another level in the hierarchy is a cache memory.
Gara teaches prefetching from other levels of cache in a memory hierarchy (see e.g. para. [0040-3]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sassone and Gara such that the memory at another level in the hierarchy is a cache memory. This would have provided the clearly predictable result of performing the exact same prefetching but from a different memory location. The use of an L2 cache also would have provided additional cache storage to improve the likelihood of hits for memory requests to improve overall memory access speed and response.
Regarding claim 2, Sassone in view of Gara teaches or suggests:
The device of claim 1, wherein: the processor core is configured to cause the circuit to retrieve the subset of the set of data in response to an instruction; and the instruction specifies the amount of the set of data to fetch ahead (see e.g. Sassone para. [0032], loop instruction).
Regarding claim 4, Sassone in view of Gara teaches or suggests:
The device of claim 2, wherein: the instruction is a first instruction; and the processor core is configured to retrieve the data element from the circuit in response to a second instruction (see e.g. Sassone para. [0031-4], a loop containing a plurality of instructions including a last instruction of the loop).
Regarding claim 5, Sassone in view of Gara teaches or suggests:
The device of claim 2, wherein the instruction specifies the set of data by specifying counts for a set of nested loops (see e.g. Sassone para. [0031-4]).
Regarding claim 7, Sassone in view of Gara teaches or suggests:
The device of claim 1, wherein: the circuit includes a register configured to store the data element; and the processor core is configured to retrieve the data element from the register of the circuit (see e.g. Gara para. [0042]).
Regarding claim 10, Sassone in view of Gara teaches or suggests:
The device of claim 1, wherein: the cache memory is a level-two (L2) cache memory; and the circuit is coupled between the processor core and the L2 cache memory in parallel with a level-one (L1) cache memory (see e.g. Gara para. [0040-3]).
Claims 11-12 are rejected for reasons corresponding to those given above for claims 1-2, 5 (see also Sassone para. [0028-9], prefetching based on generated addresses).
Claims 15-18 are rejected for reasons corresponding to those given above for claims 1-2, 4-5.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sassone in view of Gara, further in view of Diefendorff et al., US Patent Application Publication 2007/0055824 (hereinafter Diefendorff).
Regarding claim 3, Sassone in view of Gara teaches or suggests:
The device of claim 2.
Sassone in view of Gara fails to explicitly teach further comprising a template register, wherein: the template register is configured to store a value that specifies the amount of the set of data to fetch ahead; and the instruction specifies the amount of the set of data to fetch ahead by specifying the template register.
Diefendorff teaches using a stream descriptor (template register) that stores a value that specifies the amount of data to fetch ahead (see e.g. para. [0061]), and an instruction that specifies the stream descriptor (see e.g. fig. 4, 5, para. [0049]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sassone, Gara, and Diefendorff to include a template register, wherein: the template register is configured to store a value that specifies the amount of the set of data to fetch ahead; and the instruction specifies the amount of the set of data to fetch ahead by specifying the template register. This would have provided an advantage such as discussed by Diefendorff: “Advantageously, a programmer also, if he knows the configuration of the hierarchy of the cache memories in memory subsystem 104 and the size of each cache, can tailor the stream_fetch-ahead_distance 612 and cache_level indicator 802 to avoid wasting memory bandwidth and overrunning the specified cache, thereby avoiding needlessly evicting other useful data, including prefetched stream data” (see para. [0076]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sassone in view of Gara, further in view of Moyer, US Patent Application Publication 2005/0053012 (hereinafter Moyer).
Regarding claim 6, Sassone in view of Gara teaches or suggests:
The device of claim 5.
Sassone in view of Gara fails to explicitly teach wherein the instruction further specifies the set of data by specifying a data size for each element of the set of data.
Moyer teaches an instruction specifying a data size for elements of a set of data (see e.g. para. [0045-6]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sassone, Gara, and Moyer such that the instruction further specifies the set of data by specifying a data size for each element of the set of data. This would have provided advantages such as discussed by Moyer to “allow for reduced software complexity while still improving execution efficiency” (see para. [0019]).
Claims 8-9, 13-14, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sassone in view of Gara, further in view of Symes et al., US Patent Application Publication 2009/0254736 (hereinafter Symes).
Regarding claim 8, Sassone in view of Gara teaches or suggests:
The device of claim 7, wherein the circuit includes: an interface coupled to the cache memory and configured to retrieve the subset of the set of data from the cache memory (see e.g. Gara fig. 4).
Sassone in view of Gara fails to explicitly teach a butterfly network coupled between the interface and the register and configured to perform an operation on the subset of the set of data.
Symes teaches using a butterfly network to perform an operation on data retrieved from memory (see e.g. fig. 2, 3A, para. [0062-3]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sassone, Gara, and Symes to include a butterfly network coupled between the interface and the register and configured to perform an operation on the subset of the set of data. This would have provided an advantage such as discussed by Symes of increased efficiency for rearrangement operations (see e.g. para. [0013]).
Regarding claim 9, Sassone in view of Gara and Symes teaches or suggests:
The device of claim 8, wherein the operation is from a group consisting of: rotation (see e.g. Symes fig. 2, 3A, para. [0062-3]), promotion, swapping of real and imaginary components, and conversion between big endian and little endian.
Claims 13-14 are rejected for reasons corresponding to those given above for claims 8-9.
Claims 19-20 are rejected for reasons corresponding to those given above for claims 8-9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN M LINDLOF/ Primary Examiner, Art Unit 2183
Prosecution Insights