Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-11 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-11 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Yeh et al. US Patent. No. 10566348.
As per claim 1, Figs. 1-2 , 4, 9, 23 of Yeh are directed to a memory device, comprising: first main plugs (connecting to 3641 and 3651) formed in a vertical direction over a substrate and arranged in a first direction (Y0); second main plugs (connecting to 3643 and 3653) arranged substantially in parallel with the first main plugs; third main plugs (connecting to 3642 and 3652 )arranged in the first direction between the first and second main plugs, the third main plugs adjacent to the first and second main plugs in a diagonal direction (A direction, Fig. 23); and bit lines (3641-3643 and 3651-3653, col. 13, lines 38-40, Fig. 9) spaced apart from each other above the first to third main plugs and, wherein each of the first to third main plugs includes first (2051) and second (2053, col. 11, lines 41-45, Fig. 4) sub-plugs facing each other in a second direction (X) substantially orthogonal to the first direction, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines (SSL1 and SSL3, Fig. 23), and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines (SSL0 and SSL2, Fig. 3).
As per claim 2, fig. 9 and 23 of o Yeh disclose wherein the bit lines comprise: first bit lines (3641 and 3643) coupled to the first sub-plugs included in the first and second main plugs; second bit lines (3651 and 3653) adjacent to the first bit lines and coupled to the second sub-plugs included in the first and second main plugs; third bit lines (3652) adjacent to the second bit lines and coupled to the second sub- plugs included in the third main plugs; and fourth bit lines (3642) adjacent to the third bit lines and coupled to the first sub-plugs included in the third main plugs.
As per claim 3, Figs. 4 and 7 or 9 of Yeh discloses further comprising: first contacts (3371) formed between the first sub-plugs included in the first and second main plugs and the first bit lines; second contacts (3372) formed between the second sub-plugs included in the first and second main plugs and the second bit lines; third contacts (another 3371) formed between the second sub-plugs included in the third main plugs and the third bit lines; and fourth contacts (another 3372)formed between the first sub-plugs included in the third main plugs and the fourth bit lines.
As per claim 4, Fig. 4 of Yeh discloses further comprising a channel isolation pattern (261)separating the first and second sub-plugs in the vertical direction.
As per claims 5-7, Figs. 3-4 of Yeh disclose wherein each of the first and second sub-plugs comprises: a core pillar formed in the vertical direction on the substrate (Fig. 4); a channel layer surrounding a side surface of the core pillar (Fig. 4); a tunnel isolation layer surrounding a side surface of the channel layer (Fig. 3) ; a charge trap layer (243 )surrounding a side surface of the tunnel isolation layer (Fig. 3); and a blocking layer surrounding a side surface of the charge trap layer (Fig. 3).
These limitations would be rejected under 103 rejection in view by paragraphs 44 and 110 and Figs. 1 and 6’s of EOM et al. US Pub. No. 20190148505.
As per claim 8, Fig. 9 and 23 of Yeh disclose wherein the first sub-plugs included in the first main plugs are coupled to a first select line (SSL3), wherein the second sub-plugs included in the second main plugs are coupled to a second select line (SSL0), and wherein the first and second sub-plugs included in the third main plugs, the second sub-plugs included in the first main plugs, and the first sub-plugs included in the second main plugs are coupled to a third select line (SSL1) arranged between the first and second select lines.
As per claim 9, Fig. 9 of Yeh discloses wherein the first to third select lines are formed on a same layer.
As per claims 10-11, Fig. 4 of Yeh discloses further comprising a source line, fourth select lines, and word lines stacked and spaced apart from each other between the first to third select lines and the substrate.
7. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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