DETAILED ACTION
This office action is in response to the reply filed on 09/15/2025.
Claims 17-37 are pending in the application, with claim 30 having been withdrawn. Claims 17-29 and 31-37 have therefore been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20, 27, 32, and 36-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shams (U.S. Patent 6,145,072).
Regarding claim 17, Shams discloses a computer system comprising: a hardware processor comprising multiple computing elements (Fig. 1, processor array 20), interconnection switches among the multiple computing elements (Fig. 1 a subset of switches 14, these connect the PEs 10), and input-control switches for the multiple computing elements (Fig. 1 a different subset of switches 14, these control the inputs to the processing elements - See Fig. 7, as an example the switches shown and the switch below it (between PE2.1 and PE2.2)as the input-control switches and the rest in Fig. 1 as interconnection switches), wherein each computing element in the multiple computing elements is connected to each other computing element in the multiple computing elements through at least one of the interconnection switches (Fig. 1, the computing elements are connected through at least one interconnection switch. "connect" does not require a direct connection. It could be through intermediate PEs), wherein each computing element in the multiple computing elements is connected to input through at least one of the input-control switches (Fig. 1, Fig. 7, If The In in PE1.1 is considered as input, all the Pes are connected through the switches, thus through the input-control switches to the input), wherein the interconnection switches and the input-control switches within the hardware processor form an architecture switch unit (Fig. 1) configured to reconfigure the multiple computing elements to define an arrangement of logic gates in the hardware processor for executing instructions of one or more computer programs according to received settings (The switches define the connections. Switches are made of logic gates. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20).
Regarding claim 18, Shams discloses the computer system of claim 17, wherein the computing elements comprise transistors, and the received settings define the arrangement of logic gates by forming at least one of the logic gates by connecting some of the transistors using at least one of the interconnection switches [The switches define the connections. Switches are made of logic gates of transistors. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20].
Regarding claim 19, Shams discloses the computer system of claim 17, wherein the computing elements comprise predefined logic gates, and the received setting define the arrangement of logic gates by connecting some of the predefined logic gates using at least one of the interconnection switches [The switches define the connections. Switches are made of logic gates of transistors. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20].
Regarding claim 20, Shams discloses the computer system of claim 17, comprising a second processor different from the hardware processor, the second processor having a predefined processing architecture and being configured to analyze the instructions to select the settings received by the architecture switch unit to reconfigure the multiple computing elements of the hardware processor to execute the instructions [col. 6, lines 31-34; a host controls the loading of setting values based on instructions].
Regarding claim 27, Shams discloses the computer system of claim 20, wherein the second processor is configured to run controlling software for operating the architecture switch unit [col. 6, lines 31-34; a host controls the loading of setting values based on instructions].
Regarding claim 32, Shams discloses the computer system of claim 17, wherein the computer system is configured to reconfigure the multiple computing elements to define the arrangement of the logic gates in the hardware processor for executing the instructions of the one or more computer programs according to the received settings on one clock cycle of the hardware processor [The switches define the connections. Switches are made of logic gates. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20].
Regarding claim 36, Shams discloses the computer system of claim 17, comprising a second processor different from the hardware processor, wherein the computer system is configured to reconfigure the hardware processor on a clock cycle level based on requirements of the instructions [col. 6, lines 31-34; a host controls the loading of setting values].
Regarding claim 37, Shams discloses the computer system of claim 36, wherein the second processor is remote from the hardware processor and communicates with the architecture switch unit through a network interface of the hardware processor [Fig. 1; the host is remote from the processor array].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 28-29, 31, 33, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Shams in view of Official Notice.
Regarding claim 28, Shams does not explicitly disclose that the hardware is all integrated together on a single chip. However, the examiner takes official notice that such system-on-chips and their benefits were notoriously well known at the time of the invention and such use in the system of Shams would therefore have been obvious.
Regarding claim 29, Shams does not explicitly disclose that the switches are aligned in multiple layers in a multi-layer chip. However, the examiner takes official notice that such organization of switches was notoriously well known in the art at the time of the effective filing date of the application. Such organization allows for more efficient use of silicon space and would therefore have been obvious to a person having skill in the art.
Regarding claim 31, Shams does not disclose using a generative-type AI model to determine the best settings. However, the examiner takes official notice that the practice and benefits of using AI to optimize settings in a processing system were notoriously well known at the time of the effective filing date of the application. Such use allows for better optimization based on previous behavior and would therefore have been obvious in the system of Shams.
Regarding claim 33, Shams does not explicitly disclose the use of FPGAs in the processing elements. However, the examiner takes official notice that the use of FPGAs in reconfigurable systems was notoriously well known at the time of the effective filing date of the application. Such use allows for easy reconfiguration of systems and would therefore have been obvious in the system of Shams.
Regarding claim 35, Shams discloses the computer system of claim 17, comprising a second processor different from the hardware processor, wherein the computer system is configured to reconfigure the hardware processor on a clock cycle level based on requirements of the instructions [col. 6, lines 31-34; a host controls the loading of setting values]. Shams does not explicitly disclose the use of FPGAs in the processing elements. However, the examiner takes official notice that the use of FPGAs in reconfigurable systems was notoriously well known at the time of the effective filing date of the application. Such use allows for easy reconfiguration of systems and would therefore have been obvious in the system of Shams.
Allowable Subject Matter
Claims 21-26, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/COREY S FAHERTY/Primary Examiner, Art Unit 2183