DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 17 has been amended.
Claims 17-29 and 31-37 have been examined.
Examiner’s Note
Claim 31 is improperly ordered. As stated at MPEP § 608.01(n)(IV), “A claim which depends from a dependent claim should not be separated therefrom by any claim which does not also depend from said "dependent claim."” In this case claim 31 depends from dependent claim 20 and is separated therefrom by claims 29 and 30, which do not. This could be addressed by amending claim 31 to depend from claim 17 and correcting the antecedent basis for the second processor. Alternatively, the Applicant can take no action and the Examiner can reorder the claims if and when the application is allowed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20, 27, 32, and 36-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. Shams (U.S. Patent 6,145,072).
Regarding claim 17, Shams discloses:
a computer system comprising: a hardware processor comprising multiple computing elements (Fig. 1, processor array 20), interconnection switches among the multiple computing elements (Fig. 1 a subset of switches 14, these connect the PEs 10), and input-control switches for the multiple computing elements (Fig. 1 a different subset of switches 14, these control the inputs to the processing elements - See Fig. 7, as an example the switches shown and the switch below it (between PE2.1 and PE2.2) as the input-control switches and the rest in Fig. 1 as interconnection switches),
wherein each computing element in the multiple computing elements is connected to each other computing element in the multiple computing elements through at least one of the interconnection switches, wherein the interconnection switches are configured to activate interconnections between the multiple computing elements (Fig. 1, the computing elements are connected through at least one interconnection switch. "connect" does not require a direct connection. It could be through intermediate PEs. Connecting discloses activating interconnections.),
wherein each computing element in the multiple computing elements is connected to input through at least one of the input-control switches, wherein the input-control switches are configured to activate inputs to the multiple computing elements (Fig. 1, Fig. 7, If The In in PE1.1 is considered as input, all the Pes are connected through the switches, thus through the input-control switches to the input. Connecting to the input discloses being configured to activate inputs.),
wherein the interconnection switches and the input-control switches within the hardware processor form an architecture switch unit (Fig. 1) configured to reconfigure the multiple computing elements to define an arrangement of logic gates in the hardware processor for executing instructions of one or more computer programs according to received settings (The switches define the connections. Switches are made of logic gates. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20).
Regarding claim 18, Shams discloses:
the computer system of claim 17, wherein the computing elements comprise transistors, and the received settings define the arrangement of logic gates by forming at least one of the logic gates by connecting some of the transistors using at least one of the interconnection switches [The switches define the connections. Switches are made of logic gates of transistors. The memory address received every cycle as the setting. Column 5 lines 23-34 disclose executing operations by the array 20].
Regarding claim 19, Shams discloses:
the computer system of claim 17, wherein the computing elements comprise predefined logic gates, and the received setting define the arrangement of logic gates by connecting some of the predefined logic gates using at least one of the interconnection switches [The switches define the connections. Switches are made of logic gates of transistors. The memory address received every cycle as the setting. Column 5 lines 23 - 34 disclose executing operations by the array 20].
Regarding claim 20, Shams discloses:
the computer system of claim 17, comprising a second processor different from the hardware processor, the second processor having a predefined processing architecture and being configured to analyze the instructions to select the settings received by the architecture switch unit to reconfigure the multiple computing elements of the hardware processor to execute the instructions [col. 6, lines 31-34; a host controls the loading of setting values based on instructions].
Regarding claim 27, Shams discloses:
the computer system of claim 20, wherein the second processor is configured to run controlling software for operating the architecture switch unit [col. 6, lines 31-34; a host controls the loading of setting values based on instructions].
Regarding claim 32, Shams discloses:
the computer system of claim 17, wherein the computer system is configured to reconfigure the multiple computing elements to define the arrangement of the logic gates in the hardware processor for executing the instructions of the one or more computer programs according to the received settings on one clock cycle of the hardware processor [The switches define the connections. Switches are made of logic gates. The memory address received every cycle as the setting. Column 5 lines 23 -34 disclose executing operations by the array 20].
Regarding claim 36, Shams discloses:
the computer system of claim 17, comprising a second processor different from the hardware processor, wherein the computer system is configured to reconfigure the hardware processor on a clock cycle level based on requirements of the instructions [col. 6, lines 31-34; a host controls the loading of setting values].
Regarding claim 37, Shams discloses:
the computer system of claim 36, wherein the second processor is remote from the hardware processor and communicates with the architecture switch unit through a network interface of the hardware processor [Fig. 1; the host is remote from the processor array].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 28-29, 31, 33, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Shams in view of Official notice
Regarding claim 28, Shams does not explicitly disclose that the hardware is all integrated
together on a single chip. However, the examiner takes official notice that such system-on-chips and their benefits were notoriously well known at the time of the invention and such use in the system of Shams would therefore have been obvious.
Regarding claim 29, Shams does not explicitly disclose that the switches are aligned in multiple layers in a multi-layer chip. However, the examiner takes official notice that such organization of switches was notoriously well known in the art at the time of the effective filing date of the application. Such organization allows for more efficient use of silicon space and would therefore have been obvious to a person having skill in the art.
Regarding claim 31, Shams does not disclose using a generative-type AI model to determine the best settings. However, the examiner takes official notice that the practice and benefits of using AI to optimize settings in a processing system were notoriously well known at the time of the effective filing date of the application. Such use allows for better optimization based on previous behavior and would therefore have been obvious in the system of Shams.
Regarding claim 33, Shams does not explicitly disclose the use of FPGAs in the processing elements. However, the examiner takes official notice that the use of FPGAs in reconfigurable systems was notoriously well known at the time of the effective filing date of the application. Such use allows for easy reconfiguration of systems and would therefore have been obvious in the system of Shams.
Regarding claim 35, Shams discloses:
the computer system of claim 17, comprising a second processor different from the hardware processor, wherein the computer system is configured to reconfigure the hardware processor on a clock cycle level based on requirements of the instructions [col. 6, lines 31-34; a host controls the loading of setting values].
Shams does not explicitly disclose the use of FPGAs in the processing elements. However, the examiner takes official notice that the use of FPGAs in reconfigurable systems was notoriously well known at the time of the effective filing date of the application. Such use allows for easy reconfiguration of systems and would therefore have been obvious in the system of Shams.
Allowable Subject Matter
Claims 21-26, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On page 7 of the response filed June 22, 2026 (“response”), the Applicant argues, “Shams switches 14 are used to select which of the inputs to route to the outputs. For example, Shams recites "one Processing Element 10 can receive data from its North Neighbor while another is receiving data from its West neighbor, depending on the local switch settings. An example implementation of this switch 14 is shown in FIG. 3 using a multiplexer 48 and demultiplexer 50 to select one of four inputs and route the data to one of four outputs 54." Shams 7:10-16. As such, the multiplexer/demultiplexer architecture in Shams is directed to routing communications between processing elements and does not disclose or suggest the claimed "interconnection switches among the multiple computing elements" and "input-control switches for the multiple computing elements," as claimed.”
Though fully considered, the Examiner respectfully disagrees. The Applicant states that the mux/demux architecture, which is a switch, is directed to routing communications between computing elements and concludes that the switch therefore does not disclose the claimed interconnection switches and input-control switches. Switches, as disclosed by Shams, inarguably connect processing elements so that data can be routed between the processing elements. Some of the switches provide input data. This is evident from the fact that without input data, the processor would be essentially useless. Therefore, at least one of the switches disclosed by Shams, i.e., a switch via which input data is received such as the switch shown in Figure 7, is properly considered an input-control switch. Other switches provide data paths between processing elements. For example, Figure 6a of Shams discloses a path through the array of processing elements. The path is understood to be implemented using switches, i.e., interconnection switches. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 7 of the response the Applicant argues, “the Office incorrectly asserts that Shams' "subset of switches 14" discloses or suggests the previously recited claimed feature of "wherein the interconnection switches and the input-control switches within the hardware processor form an architecture switch unit configured to reconfigure the multiple computing elements to define an arrangement of logic gates in the hardware processor for executing instructions of one or more computer programs according to received settings." Office Action, p. 2, emphasis added. However, Shams does not disclose or suggest that "the interconnection switches are configured to activate interconnections between the multiple computing elements" and that "the input-control switches are configured to activate inputs to the multiple computing elements," as newly claimed. Emphasis added. Rather, Shams's switches 14 perform different functions than the claimed "interconnection switches" and "input-control switches." Shams describes that the switches 14 are used to "connect[] one Processing Element 10 to three of its eight nearest neighbors" and that the "dynamically reconfigurable switch 14 allows for communication between four nearest-neighbor Processing Elements 10 while only requiring at least one I/O connection 54 to each Processing Element 10." Shams 6:57-60. Shams does not disclose that any of its subset of switches is configured to "activate interconnections between the multiple computing elements" while a different subset of switches is "configured to activate inputs to the multiple computing elements," as required by the claims.”
Though fully considered, the Examiner respectfully disagrees. Shams discloses, at col. 7, lines 24-27, “The interprocessor communications between processing elements in the processing array are performed through Dynamically Reconfigurable Switches (DRS).” The Examiner maintains that this discloses, “interconnection switches are configured to activate interconnections between the multiple computing elements.” The Applicant has failed to indicate any purported difference between performing interprocessor communications and activating interconnections between multiple computing elements. Furthermore, as discussed above, each processing element has an input register, which discloses that at least some of the switches provide input. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 8 of the response the Applicant argues, “Shams switches 14 do not "form an architecture switch unit configured to reconfigure the multiple computing elements to define an arrangement of logic gates in the hardware processor for executing instructions of one or more computing programs according to received settings," as required by the claims. Emphasis added. As a result, the presently claimed architecture switch unit includes separate switch sets that selectively activate interconnections between computing elements and selectively activate inputs to computing elements. Through the operation of these switch sets, the hardware processor can be reconfigured to define different arrangements of logic gates for execution of different instruction sets, such as performing any desired operations in the future.”
Though fully considered, the Examiner respectfully disagrees. Shams explicitly discussed ynamic reconfiguration throughout the patent, from the title to the claims. See, for example, Figures 6a and 6b, and related description, which disclose dynamically reconfiguring the processing array to form custom patterns of processing elements based on program needs. The Examiner maintains that this teaches the limitations in question. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 8 of the response the Applicant argues, “Applicant traverses the various instances of apparent "Official Notice" that some claim elements were "well known." See, e.g., Office Action at pp. 5-6. Under the law, the Office Action's conclusions that the practice and benefits of various claim features were "well known" must be supported by "documentary evidence"-a critical shortcoming in the rejections here. K/S Himpp v. Hear-Wear Technologies, LLC, 751 F.3d 1362, 1366 (Fed. Cir. 2014) (holding that the Patent Office "cannot accept general conclusions about what is 'basic knowledge' or 'common sense' as a replacement for documentary evidence for core factual findings in a determination of patentability.... To hold otherwise would be to embark down a slippery slope which would permit the examining process to deviate from the well-established and time-honored requirement that rejections be supported by evidence."). Worse yet, the instances of "Official Notice" in the Office Action are nothing more than unsupported assumptions that are untethered from the particular structural combinations recited therein; Applicant disagrees with respect to these particular claim combinations and notes that any future rejection relying on these conclusions must be supported with "documentary evidence." MPEP § 2144.03(C) (noting that the Patent Office "must point to some concrete evidence" in order to support such a rejection).”
Though fully considered, the Examiner respectfully disagrees. The Applicant’s traversal of official notice is improper and inadequate. As stated at MPEP § 2144.03(c), “To adequately traverse a finding based on official notice, an applicant must specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art. A mere request by the applicant that the examiner provide documentary evidence in support of an officially-noticed fact is not a proper traversal.” The Applicant has not pointed out any supposed error or stated that any of the facts in question are not common knowledge, much less why the facts are not considered common knowledge. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 8-9 of the response the Applicant argues, “the Office indicates that Shams col. 6 lines 31-34 allegedly discloses the features of claim 20. In particular, the Office indicates that Shams's "host controls the loading of setting values based on instructions" allegedly discloses the features of claim 20. However, Shams's host computer does not "analyze instructions to select the setting ... to reconfigure the multiple computing elements of the hardware processor to execute the instructions," as claimed. Rather, Shams's host pre-loads a fixed configuration value into each switch's configuration register prior to computation and the switch settings are predetermined and static for the duration of a processing cycle. Shams, 5:55-67. This is fundamentally different from the claimed second processor of claim 20, which is "configured to analyze the instructions to select the settings received by the architecture switch unit to reconfigure the multiple computing elements of the hardware processor to execute the instructions," as claimed. As a result, Shams does not disclose or suggest the features of claim 20.”
Though fully considered, the Examiner respectfully disagrees. Shams discloses, at col. 5, lines 25-28, the host compiles programs written in high level languages and generates control information, which the host then transfers to the processing array. The Examiner maintains that his discloses analyzing instructions and selecting settings for the processing elements to reconfigure the processing elements to execute the instructions. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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