DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other Ref: Park (US 20150253998 – Memory system
Alam (US 20220139488) – Managing memory device
Non-patent Literature (attached) – Girard, Patrick, A Survey of Test and Reliability Solutions for Magnetic Random Access Memories, Proceedings of the IEEE (vol 109, Issue 2, Feb 2021), pages 149-169
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/11/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,4 are rejected under 35 U.S.C. 103 as being unpatentable over Asnaashai (US 8711631) and in view of Yu (US 20120284587) and further in view of Berger (US 20190163408) and Hwang (US 20160179421)
Claim 1. Asnaashai discloses An magnetoresistive random access memory having a work area and a boot area (eg., Fig. 2 col 4:25-39 - MRAM array 34, and MRAM array 34 of storage medias 18 includes the MRAM portion 36b of hybrid reserved area 36 and the MRAM portion 30b of hybrid user area 30; col 4:49-59 - the hybrid reserved area 36 may be entirely a part of the MRAM portion 36b. the hybrid user area 30 is entirely a part of the MRAM portion 30b. In the case where both the hybrid reserved area 36 and the hybrid user area 30 are both entirely a part of the MRAM devices 24, there is no need for the NAND devices 22… boot code), the magnetoresistive random access memory comprising:
data stored in the reliability determination area is read, (eg., col 6:3-7 - if the host wishes to read data that the controller 14 has saved in the hybrid reserved area 36 but not yet moved to the hybrid user area 30, the controller 14 knows to access this data only from the hybrid reserved area 36; col 8:15-20 - user data is moved from the MRAM portion 36b to the intended LUN and the pointer of step 128 is re-adjusted to point to a location in the LUN where the user data has been moved).
Asnaashai does not disclose, but Yu discloses
and when the read data is different from the new data, the work area and another area are switched with each other (eg., 0093 - spare and swap blocks located in flash that are involved in partial overwrites. For example, data is written to one block in the flash and later a partial of original data is changed. The controller writes the new update to the spare block in flash first. Then the old and new data will be merged into the swap block. After that the original block and the spare block will be erased.; 0288 - DRAM buffer can be substituted with NVRAM such as ..Magnetoresistive RAM (MRAM), )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, providing the benefit of extend the lifetime of individual blocks (see Yu, 0059) increased-endurance and longevity of flash memory drives (0006).
Asnaashai in view of Yu does not disclose, but Berger discloses
the work area comprising a data storage area and a reliability determination area (eg., 0066 Fig. 8 - the lower 48 KB of the MRAM are used to store the block byte replacement information in a block byte replacement partition 114; The upper part of the MRAM is used to store the block corrected error count in a block corrected error count partition 116. In this case as well, the corrected error count can store the block error corrected count for two sets of 6 die as 4-bit values allowing for up to 15 corrected errors before hitting the threshold ).
in response to data being written to the data storage area of the work area, new data that is different from old data stored in the reliability determination area is written to the reliability determination area (eg., 0066 - All bytes in this partition are initialized to all zeros. When a determination is made to replace a block, the 3-bit value of the byte to be replaced in each block is stored in the location in the MRAM. ; 0057 - warm sparing data is stored in the lower part of the MRAM, with two entries per MRAM byte. In some cases, using a 3-bit code for the die to be replaced, 96 k 3-bit entries will support all three banks of flash at the block level. The 3-bit code is sufficient to cover replacement of the die).
after the new data is written to the reliability determination area, and data indicating reliability is reduced, (eg., 0066 - When a determination is made to replace a block, the 3-bit value of the byte to be replaced in each block is stored in the location in the MRAM. When a determination is made that the block is “bad” the 3-bit value is changed to 111).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, providing the benefit of eliminating the need for additional EEPROM components (see Berger, 0065) a cost-effective warm sparing approach is used to achieve high levels of fault tolerance with less components. In certain applications, the recorder can achieve excellent performance for mission lifetimes of five years and beyond (0068) a method of providing flash memory data recorders with high-reliability (0001).
Asnaashai in view of Yu and Berger does not disclose, but Hwang discloses
the processor transfers data of an operating system stored in the boot area to the work area (eg., Fig. 8 0111 - when a storage reliability level of a memory area storing specific data is changed into another storage reliability level, the specific data may be moved to another memory area having a storage reliability level corresponding to a required reliability level of the specific data. 0112 - the process of moving the data HD1 and HD2 may be performed immediately after the storage reliability level is changed).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, with Hwang providing the benefit of As a storage device or a storage system is damaged, the life of the storage device or the storage system may come to an end. When the life of the storage device or the storage system comes to an end, the storage device or the storage system may not store data normally. The time period for using the storage device or the storage system needs to be extended, in order to reliably store data (see Hwang, 0007, 0008).
Claim 4. Asnaashai discloses
wherein the boot area is an area for storing an operating system (eg., col 7:32-36 Fig. 3, 5 - MRAM portion 36b of hybrid reserved area 36 is shown, as an exemplary embodiment, to include the boot code, tables and data cache which are frequently accessed by the controller and effect system performance), and
the data storage area of the work area is an area for storing data that is handled in a process performed by the operating system (eg., col 4:39 - MRAM portion 30b of hybrid user area 30.; col 4:50-54 hybrid user area 30 is entirely a part of the MRAM portion 30b. In the case where both the hybrid reserved area 36 and the hybrid user area 30 are both entirely a part of the MRAM devices 24)
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Asnaashai (US 8711631) and in view of Yu (US 20120284587) and further in view of Berger (US 20190163408) and Hoya (US 20150074491) and Hwang (US 20160179421)
Claim 5. Asnaashai discloses An magnetoresistive random access memory having a work area, a boot area (eg., Fig. 2 col 4:25-39 - MRAM array 34, and MRAM array 34 of storage medias 18 includes the MRAM portion 36b of hybrid reserved area 36 and the MRAM portion 30b of hybrid user area 30; col 4:49-59 - the hybrid reserved area 36 may be entirely a part of the MRAM portion 36b. the hybrid user area 30 is entirely a part of the MRAM portion 30b. In the case where both the hybrid reserved area 36 and the hybrid user area 30 are both entirely a part of the MRAM devices 24, there is no need for the NAND devices 22… boot code), the magnetoresistive random access memory comprising:
data stored in the reliability determination area is read, (eg., col 6:3-7 - if the host wishes to read data that the controller 14 has saved in the hybrid reserved area 36 but not yet moved to the hybrid user area 30, the controller 14 knows to access this data only from the hybrid reserved area 36; col 8:15-20 - user data is moved from the MRAM portion 36b to the intended LUN and the pointer of step 128 is re-adjusted to point to a location in the LUN where the user data has been moved).
Asnaashai does not disclose, but Yu discloses
and when the read data is different from the new data, the work area and the unused area are switched with each other (eg., 0093 - spare and swap blocks located in flash that are involved in partial overwrites. For example, data is written to one block in the flash and later a partial of original data is changed. The controller writes the new update to the spare block in flash first. Then the old and new data will be merged into the swap block. After that the original block and the spare block will be erased.; 0288 - DRAM buffer can be substituted with NVRAM such as ..Magnetoresistive RAM (MRAM), )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, providing the benefit of extend the lifetime of individual blocks (see Yu, 0059) increased-endurance and longevity of flash memory drives (0006).
Asnaashai in view of Yu does not disclose, but Berger discloses
the work area comprising a data storage area and a reliability determination area (eg., 0066 Fig. 8 - the lower 48 KB of the MRAM are used to store the block byte replacement information in a block byte replacement partition 114; The upper part of the MRAM is used to store the block corrected error count in a block corrected error count partition 116. In this case as well, the corrected error count can store the block error corrected count for two sets of 6 die as 4-bit values allowing for up to 15 corrected errors before hitting the threshold ).
in response to data being written to the data storage area of the work area, new data that is different from old data stored in the reliability determination area is written to the reliability determination area (eg., 0066 - All bytes in this partition are initialized to all zeros. When a determination is made to replace a block, the 3-bit value of the byte to be replaced in each block is stored in the location in the MRAM. ; 0057 - warm sparing data is stored in the lower part of the MRAM, with two entries per MRAM byte. In some cases, using a 3-bit code for the die to be replaced, 96 k 3-bit entries will support all three banks of flash at the block level. The 3-bit code is sufficient to cover replacement of the die).
after the new data is written to the reliability determination area, and when the read data is different from the new data indicating reliability is reduced (eg., 0066 - When a determination is made to replace a block, the 3-bit value of the byte to be replaced in each block is stored in the location in the MRAM. When a determination is made that the block is “bad” the 3-bit value is changed to 111).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, providing the benefit of eliminating the need for additional EEPROM components (see Berger, 0065) a cost-effective warm sparing approach is used to achieve high levels of fault tolerance with less components. In certain applications, the recorder can achieve excellent performance for mission lifetimes of five years and beyond (0068) a method of providing flash memory data recorders with high-reliability (0001).
Asnaashai in view of Yu and Berger does not disclose, but Hoya discloses
an unused area reserved for future use (eg., 0021-0025 - A magnetic tunnel junction (MTJ) element is used here as the magnetoresistive element ; FIG. 2, the MTJ element includes a storage layer 1, a reference layer 3, and a tunnel barrier layer 2 arranged between the storage layer 1 and the reference layer 3.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, providing the benefit of data is read from the memory cell array 11, and error checking and correction of the read data is performed. Immediately after the error checking and correction, the data is written back to the address (memory cell) at which error data has been detected. This makes it possible to reduce data errors caused by read disturb and write errors (see Hoya, 0035).
Asnaashai in view of Yu and Berger and Hoya does not disclose, but Hwang discloses
the processor transfers data of an operating system stored in the boot area to the work area (eg., Fig. 8 0111 - when a storage reliability level of a memory area storing specific data is changed into another storage reliability level, the specific data may be moved to another memory area having a storage reliability level corresponding to a required reliability level of the specific data. 0112 - the process of moving the data HD1 and HD2 may be performed immediately after the storage reliability level is changed).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, and Hoya with Hwang providing the benefit of As a storage device or a storage system is damaged, the life of the storage device or the storage system may come to an end. When the life of the storage device or the storage system comes to an end, the storage device or the storage system may not store data normally. The time period for using the storage device or the storage system needs to be extended, in order to reliably store data (see Hwang, 0007, 0008).
Claim 6. Asnaashai discloses
wherein the boot area is an area for storing an operating system (eg., col 7:32-36 Fig. 3, 5 - MRAM portion 36b of hybrid reserved area 36 is shown, as an exemplary embodiment, to include the boot code, tables and data cache which are frequently accessed by the controller and effect system performance), and
the data storage area of the work area is an area for storing data that is handled in a process performed by the operating system (eg., col 4:39 - MRAM portion 30b of hybrid user area 30.; col 4:50-54 hybrid user area 30 is entirely a part of the MRAM portion 30b. In the case where both the hybrid reserved area 36 and the hybrid user area 30 are both entirely a part of the MRAM devices 24)
Response to Arguments
Applicant's arguments filed 6/11/2026 have been fully considered but they are not persuasive.
For claims 1 and 5, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Asnaashai in view of Yu and Berger does not disclose, but Hwang discloses
the processor transfers data of an operating system stored in the boot area to the work area (eg., Fig. 8 0111 - when a storage reliability level of a memory area storing specific data is changed into another storage reliability level, the specific data may be moved to another memory area having a storage reliability level corresponding to a required reliability level of the specific data. 0112 - the process of moving the data HD1 and HD2 may be performed immediately after the storage reliability level is changed).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the MRAM with portions for boot and user data as disclosed by Asnaashai, with Yu, with Berger, with Hwang providing the benefit of As a storage device or a storage system is damaged, the life of the storage device or the storage system may come to an end. When the life of the storage device or the storage system comes to an end, the storage device or the storage system may not store data normally. The time period for using the storage device or the storage system needs to be extended, in order to reliably store data (see Hwang, 0007, 0008).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1 and 5, which are addressed above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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