Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 3, 9, 13-15, 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al. (CN 112310227 A) hereafter referred to as Luo
In regard to claim 1 Luo teaches a [see “Embodiment 1” “As shown in FIG. 1f, the high barrier SiC JBS device”] semiconductor device, comprising:
a substrate [“SiC substrate”];
an epitaxial layer [“N-SiC epitaxial layer”], located on one side [top] of the substrate, wherein a doped region [“performing surface P-type impurity shallow injection (P-injection) on the etching area, forming N-doped region” “performing P-type impurity deep injection (P + injection) to the etching area … forming a junction barrier region in the active region, at the same time, forming a terminal region”] is formed on a surface of the epitaxial layer that is away from the substrate, and the epitaxial layer comprises an active region [see “the N-SiC epitaxial layer comprises a junction barrier region extending into the epitaxial layer from the upper surface of the epitaxial layer and a terminal region located at the periphery of the junction barrier region”] and a termination region [see “terminal region” is in the entire “periphery of the junction barrier region”] that surrounds the active region;
a passivation layer [“depositing and growing a SiO2 medium layer” “passivation medium”], covering the termination region and on which a window [ “photoetching the surface medium of step 3 A, etching, only keeping the medium layer on the terminal area” thus creating the window, see Fig. 1f] corresponding to the active region is formed; and
a metal layer [“depositing and sputtering the metal Ti on the surface of the wafer” “the metal layer, etching, only remaining the upper surface of the junction barrier region is covered by metal, forming a second electrode layer” “thickening the first electrode layer and the second electrode layer” , see final electrode shape see Fig. 1f], covering the window and an inner edge of the passivation layer that forms the window, and forming a schottky contact [“annealing treatment for the wafer obtained in step 3 D for 5min-10min at 400-600 degrees centigrade, forming a Schottky contact between the SiC and the metal”] with the active region in the window.
In regard to claim 6 Luo teaches further comprising: a protective layer [see Fig. 1f “Step six: performing PI curing on the upper surface of the dielectric layer; forming a PI layer”], covering the passivation layer and an outer edge of the metal layer.
Claim(s) 7, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al. (CN 112310227 A) hereafter referred to as Luo
In regard to claim 7 Luo teaches a semiconductor device [see “Embodiment 1” “As shown in FIG. 1f, the high barrier SiC JBS device”] manufacturing method comprising:
forming a doped region [“performing surface P-type impurity shallow injection (P-injection) on the etching area, forming N-doped region” “performing P-type impurity deep injection (P + injection) to the etching area … forming a junction barrier region in the active region, at the same time, forming a terminal region”] on a surface [top] of an epitaxial layer [“N-SiC epitaxial layer”] that is away from a substrate [“SiC substrate”],
wherein the epitaxial layer is located on one side [top] of the substrate and comprises an active region [see “the N-SiC epitaxial layer comprises a junction barrier region extending into the epitaxial layer from the upper surface of the epitaxial layer and a terminal region located at the periphery of the junction barrier region”] and a termination region [see “terminal region” is in the entire “periphery of the junction barrier region”] that surrounds the active region;
disposing a passivation layer [“depositing and growing a SiO2 medium layer” “passivation medium”] on the termination region, wherein the passivation layer has a window [ “photoetching the surface medium of step 3 A, etching, only keeping the medium layer on the terminal area” thus creating the window, see Fig. 1f], and the window corresponds to the active region; and
disposing a metal layer [“depositing and sputtering the metal Ti on the surface of the wafer” “the metal layer, etching, only remaining the upper surface of the junction barrier region is covered by metal, forming a second electrode layer” “thickening the first electrode layer and the second electrode layer” , see final electrode shape see Fig. 1f] on the window and on an inner edge of the passivation layer that forms the window, wherein the metal layer forms a schottky contact [“annealing treatment for the wafer obtained in step 3 D for 5min-10min at 400-600 degrees centigrade, forming a Schottky contact between the SiC and the metal”] with the active region in the window.
In regard to claim 10 Luo teaches further comprising: disposing a protective layer [see Fig. 1f “Step six: performing PI curing on the upper surface of the dielectric layer; forming a PI layer”] on the passivation layer and on an outer edge of the metal layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 4, 5, 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Allen et al. (US 20040159865 A1) hereafter referred to as Allen
In regard to claim 2 Luo does not teach wherein the passivation layer further comprises a first passivation layer, a second passivation layer, and a third passivation layer that are stacked in sequence and disposed in contact with each other.
See Allen “an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs” “Prior to formation of contacts 20, 22, 24 and 40, the upper surface of the device is preferably passivated with an Oxide-Nitride-Oxide (ONO) passivation layer 60. As seen in FIG. 4, the upper surface of the structure is passivated by growing a thermal oxide layer 60A of SiO.sub.2, followed by depositing a Si.sub.3N.sub.4 layer 60B using PECVD or LPCVD, followed by a final layer of thermally grown SiO.sub.2 60C” “The ONO passivation layer enables the device to have better power density, primarily due to decreased trapping from the surface. ONO has lower interface trap density (D.sub.it) near the conduction band”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Luo to include wherein the passivation layer further comprises a first passivation layer, a second passivation layer, and a third passivation layer that are stacked in sequence and disposed in contact with each other.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain better passivation for SiC.
In regard to claim 4 Luo and Allen as combined teaches [see combination “growing a thermal oxide layer 60A of SiO.sub.2, followed by depositing a Si.sub.3N.sub.4 layer 60B using PECVD or LPCVD, followed by a final layer of thermally grown SiO.sub.2 60C”] wherein the material of the first passivation layer and the material of the third passivation layer are the same and comprise silicon oxide.
In regard to claim 5 Luo and Allen as combined teaches [see combination “SiO.sub.2 layer may also be formed to a thickness of from about 50 to about 500 .ANG.” “Si.sub.3N.sub.4 may be deposited to a thickness of from about 200 to about 2000 .ANG.” “Si.sub.3N.sub.4 layer may be oxidized to provide an oxide layer having a thickness of from about 20 to about 200 .ANG.”] wherein a thickness of the third passivation layer is less than a thickness of the first passivation layer and a thickness of the second passivation layer.
In regard to claim 11 Luo and Allen as combined teaches wherein the material of [see combination “growing a thermal oxide layer 60A of SiO.sub.2, followed by depositing a Si.sub.3N.sub.4 layer 60B using PECVD or LPCVD, followed by a final layer of thermally grown SiO.sub.2 60C”] the second passivation layer comprises silicon nitride.
In regard to claim 12 Luo and Allen as combined teaches wherein the first passivation layer is located between [see Luo Fig. 1f passivation, see combination] the epitaxial layer and the second passivation layer, and a material of the second passivation layer is different [see combination “growing a thermal oxide layer 60A of SiO.sub.2, followed by depositing a Si.sub.3N.sub.4 layer 60B using PECVD or LPCVD, followed by a final layer of thermally grown SiO.sub.2 60C”] from both a material of the first passivation layer and a material of the third passivation layer.
Claim(s) 8, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Allen et al. (US 20040159865 A1) hereafter referred to as Allen
In regard to claim 8 Luo does not teach wherein the passivation layer comprises a first passivation layer, a second passivation layer, and a third passivation layer, and disposing the passivation layer on the termination region further comprises: forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer, wherein a material of the first dielectric layer is different from a material of the second dielectric layer.
See Allen “an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs” “Prior to formation of contacts 20, 22, 24 and 40, the upper surface of the device is preferably passivated with an Oxide-Nitride-Oxide (ONO) passivation layer 60. As seen in FIG. 4, the upper surface of the structure is passivated by growing a thermal oxide layer 60A of SiO.sub.2, followed by depositing a Si.sub.3N.sub.4 layer 60B using PECVD or LPCVD, followed by a final layer of thermally grown SiO.sub.2 60C” “The ONO passivation layer enables the device to have better power density, primarily due to decreased trapping from the surface. ONO has lower interface trap density (D.sub.it) near the conduction band”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Luo to include wherein the passivation layer comprises a first passivation layer, a second passivation layer, and a third passivation layer, and disposing the passivation layer on the termination region further comprises: forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer, wherein a material of the first dielectric layer is different from a material of the second dielectric layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain better passivation for SiC.
In regard to claim 16 Luo and Allen as combined teaches further comprising: etching a second window [see Luo “photoetching the surface medium of step 3 A, etching, only keeping the medium layer on the terminal area” thus creating the window, see Fig. 1f, see combination this is done on the passivation taught by Allen] on a portion of the second dielectric layer that corresponds to the active region to form the second passivation layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
For claims 3, 5 structure, see IDS reference Guo et al. (CN 113451127 A) teaches power device and see Fig. 8 see “Schottky metal layer 720” “field oxide layer 300” “the material of the first sub-layer 410 is silicon nitride. In some embodiments, the material of the second sub-layer 420 is silicon oxide”, see Abstract “when performing the reliability test, the first passivation layer will not crack due to metal layer deformation, so as to enhance the power device anti-steam erosion capability, improves the reliability of the power device in the high temperature and high humidity environment for a long time work” see Guo Fig. 8 see the window in “field oxide layer 300” is inside the window in first sub-layer 410, “the thickness of the field oxide layer 300 may be 1 μ m to 1.5 μ m” “thickness of the first sub-layer 410 is 0.5 μ m to 0.7 μ m, such as 0.5 μ m, 0.6 μ m, 0.7 μ m and so on. In some embodiments, the thickness of the second sub-layer 420 is 0.1 μ m to 0.2 μ m, such as 0.1 μ m, 0.15 μ m, 0.2 μ m and so on. In some embodiments, the thickness of the second passivation layer 500 is 0.05 μ m to 0.1 μ m” .
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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