DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10, 13, 16-17, 22, and 27-32 are pending and examined in this application wherein claim 1 is independent claim.
Claims 11-12, 14-15, 18-21, and 23-26 are preliminary cancelled.
Claim Objections
Claim 4 is objected to because of the following informalities:
Re claim 4, the limitation “the third architecture bloc;” in line 10 should be “the third architecture block;”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 13, 16-17 and 27-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budovski et al. (U.S. 2022/0382578) in view of Danilak (U.S. 2020/0057642).
Re claim 1, Budovski et al. disclose in Figures 1-8 a microprocessor including a function-specific architecture (e.g. abstract, Figures 1-2, and paragraphs [0061 and 0157-0158] with the microprocessor architectures of multi-cores processor), the microprocessor comprising: an interface configured to communicate with an external memory via at least one memory channel (e.g. Figure 1 and paragraphs [0034-0035, 0042 and 0167] wherein an communication interface is applied to communicate with internal and external memory/database); a first architecture block configured to perform a first task associated with a thread (e.g. Figure 2 with core architecture for handling parent task A or child task X, Y…); a second architecture block configured to perform a second task associated with the thread (e.g. Figure 2 with core architecture for handling child task X…), wherein the second task includes a memory access via the at least one memory channel (e.g. paragraphs [0034-0035, 0167 and 0177] wherein all these tasks parent/children tasks need to access the memory/database for processing); and a third architecture block configured to perform a third task associated with the thread (e.g. Figure 2 with core architecture for handling child task Y…) wherein the first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel (e.g. paragraph [0038, 0093, 0169] wherein certain tasks or architectures can be configured to operate in parallel). Budovski et al. fail to disclose wherein the first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor. Danilak discloses the first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor (e.g. Figures 4-6 and paragraphs [0016-0018, 0061, 0228] wherein multiple architectures/tasks/ALU/PEs can be configured to operate in parallel within a single cycle). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of claimed invention to add the first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor as conceptually seen in Danilak’s invention into Budovski et al.’s invention because it would enable to improve the process throughput.
Re claim 2, Budovski et al. in view of Danilak disclose in Figures 1-8 the first task includes a thread context restore operation (e.g. Budovski et al. paragraphs [0035 and 0097]).
Re claim 3, Budovski et al. in view of Danilak disclose in Figures 1-8 the third task includes a thread context store operation (e.g. Budovski et al. – paragraphs [0054-0056 and 0096] and Danilak – paragraph [0013 and 0069]).
Re claim 4, Budovski et al. in view of Danilak disclose in Figures 1-8 during a first clock cycle associated with the microprocessor and for a first retrieved thread (e.g. Budovski et al. – paragraphs [0097-0099]): a thread context restore operation is performed by the first architecture block (e.g. Budovski et al. paragraphs [0035 and 0097]), a memory access operation is performed by the second architecture block (e.g. Budovski et al. - Figures 2-3), and a thread context store operation is performed by the third architecture block (e.g. Budovski et al. – paragraphs [0054-0056 and 0096] and Danilak – paragraph [0013 and 0069]); during a second clock cycle associated with the microprocessor and for a second retrieved thread, wherein the second clock cycle immediately follows the first clock cycle, a thread context restore operation is performed by the first architecture block (e.g. Budovski et al. paragraphs [0035 and 0097]), a memory access operation is performed by the second architecture block (e.g. Budovski et al. - Figures 2-3), and a thread context store operation is performed by the third architecture bloc (e.g. Budovski et al. – paragraphs [0054-0056 and 0096] and Danilak – paragraph [0013 and 0069]); and wherein the memory access operation performed by the second architecture block during the first or second clock cycle is either a READ or a WRITE operation (e.g. Budovski et al. – paragraphs [0007 and 0096-0097]).
Re claim 5, Budovski et al. in view of Danilak disclose in Figures 1-8 the second architecture block includes a first segment configured to perform a READ memory access and a second segment configured to perform a WRITE memory access (e.g. Budovski et al. – paragraphs [0007 and 0096-0097]).
Re claim 6, Budovski et al. in view of Danilak disclose in Figures 1-8 the second architecture block is configured to perform a READ memory access via the at least one memory channel, and wherein the microprocessor further comprises a fourth architecture block configured to perform a WRITE memory access via the at least one memory channel (e.g. Budovski et al. – paragraphs [0007, 0077-0078, 0093 and 0096-0097]).
Re claim 7, Budovski et al. in view of Danilak disclose in Figures 1-8 during a first clock cycle associated with the microprocessor and for a first retrieved thread: a thread context restore operation is performed by the first architecture block (e.g. Budovski et al. paragraphs [0035 and 0097]), a READ memory access operation is performed by the second architecture block (e.g. Budovski et al. – paragraphs [0007 and 0096-0097]), and a thread context store operation is performed by the third architecture block; and during a second clock cycle associated with the microprocessor and for a second retrieved thread (e.g. Figures 2-3), wherein the second clock cycle immediately follows the first clock cycle, a WRITE memory access operation is performed by the fourth architecture block (e.g. Budovski et al. – paragraphs [0007 and 0096-0097]).
Re claim 8, Budovski et al. in view of Danilak disclose in Figures 1-8 the microprocessor further comprises a fourth architecture block configured to execute, during the single clock cycle, a data operation relative to data received as a result of an earlier completed READ request (e.g. Budovski et al. – paragraphs [0007 and 0096-0097] with the read request and Danilak - Figures 4-6 and paragraphs [0016-0018, 0061, 0228] wherein multiple architectures/tasks/ALU/PEs can be configured to operate in parallel within a single cycle).
Re claim 9, Budovski et al. in view of Danilak disclose in Figures 1-8 the data operation includes generation of a read request specifying a second memory location different from a first memory location associated with the earlier completed READ request (e.g. Budovski et al. – paragraphs [0007 and 0035-0037] with non-overlapping caching).
Re claim 10, Budovski et al. in view of Danilak disclose in Figures 1-8 one or more controllers and associated multiplexers configured to select the thread from at least one thread stack including a plurality of pending threads (e.g. Budovski et al. – paragraph [0093] with threads multiplexing).
Re claim 13, Budovski et al. in view of Danilak disclose in Figures 1-8 the at least one thread stack includes a first thread stack associated with thread read requests and a second thread stack associated with thread data returned from earlier thread read requests (e.g. Budovski et al. – paragraphs [0071 and 0094]).
Re claim 16, Budovski et al. in view of Danilak disclose in Figures 1-8 the one or more controllers and associated multiplexers are configured to cause alignment of a first memory access operation, associated with a first thread and occurring during a first clock cycle (e.g. Danilak - Figures 4-6 and paragraphs [0016-0018, 0061, 0228] wherein multiple architectures/tasks/ALU/PEs can be configured to operate in parallel within a single cycle), with a second memory access operation, associated with a second thread and occurring during a second clock cycle adjacent to the first clock cycle (e.g. Budovski et al. – Figures 2-3), wherein the first and second memory access operation is either a READ or a WRITE operation (e.g. Budovski et al. – paragraphs [0007 and 0096-0097]).
Re claim 17, Budovski et al. in view of Danilak disclose in Figures 1-8 at least one of the first task or the third task is associated with maintenance of a context associated with the thread (e.g. Budovski et al. – paragraph [0007, 0071, and 0075]).
Re claim 27, Budovski et al. in view of Danilak disclose in Figures 1-8 the microprocessor is a multi-threading microprocessor (e.g. Budovski et al. – abstract, Figures 1-2, and paragraphs [0061 and 0157-0158] with the microprocessor multithreads architectures of multi-cores processor).
Re claim 28, Budovski et al. in view of Danilak disclose in Figures 1-8 at least one of the first architecture block, the second architecture block, or the third architecture block is implemented using a field programmable gate array (e.g. Budovski et al. – paragraph [0157]).
Re claim 29, Budovski et al. in view of Danilak disclose in Figures 1-8 at least one of the first architecture block, the second architecture block, or the third architecture block is implemented using a programmable state machine, wherein the context of the state machine is stored (e.g. Budovski et al. – Figures 2-3 and paragraphs [0073-0076]).
Re claim 30, Budovski et al. in view of Danilak disclose in Figures 1-8 the first task, the second task, and the third task are associated with a key value operation (e.g. Budovski et al. – Figures 2-3 with parent and children relationship).
Re claim 31, Budovski et al. in view of Danilak disclose in Figures 1-8 the microprocessor is included as part of a hardware layer of a data analytics accelerator (e.g. Budovski et al. – paragraphs [0157]).
Re claim 32, Budovski et al. in view of Danilak disclose in Figures 1-8 the microprocessor is a pipelined processor configured to coordinate pipelined operations on a plurality of threads by context switching among the plurality of threads (e.g. Budovski et al. – paragraphs [0072 and 0082]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budovski et al. (U.S. 2022/0382578) in view of Danilak (U.S. 2020/0057642) and further in view of Sity Elad (W.O. 2019/025864).
Re claim 22, Budovski et al. in view of Danilak fail to disclose the at least one memory channel includes two or more memory channels. However, Sity Elad disclose the at least one memory channel includes two or more memory channels (e.g. paragraph [0299]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of claimed invention to add the at least one memory channel includes two or more memory channels as seen in Sity Elad’s invention into Budovski et al.’s invention because it would enable to simultaneously access the memory which improve throughput.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2026/0140757 discloses a data processing system includes a first processor, a storage device, and a second processor. The first processor includes a plurality of threads, and each thread corresponds to one data buffer. The first processor is configured to execute the plurality of threads to separately write a plurality of transaction logs into a plurality of data buffers respectively corresponding to the plurality of threads.
U.S. Patent Application Publication No. 2022/0382578 discloses asynchronous processing of transaction log requests in a database transaction log service.
W.O. Patent Application Publication No. 2022/250876 discloses asynchronous processing of transaction log requests in a database transaction log service.
W.O. Patent Application Publication No. 2019/025864 discloses distributed processors and methods for compiling code for executed by the distributed processor.
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/Chat C Do/Supervisory Patent Examiner, Art Unit 2193
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