Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendments filed on November 3, 2025. Claim 6 has been cancelled.
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a).
Priority
Acknowledgment is made of applicant's claim for foreign priority based on Korean Patent Application No. 10-2023-0112093, filed on August 25, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings submitted on November 3, 2025 have been considered and accepted.
Specification
The specification submitted on November 3, 2025 has been considered and accepted.
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, line 14 “wherein the address pointer further configured to:” should read “wherein the address pointer generation circuit is further configured to:”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lowe et al. (US 6934198 B1), hereinafter referred to as Lowe, in view of Miller et al. (U.S. patent application publication 20230087576 A1), hereinafter referred to as Miller, further in view of Cheng et al. (U.S. patent 6986004 B1), hereinafter referred to as Cheng.
Regarding claim 1, Lowe teaches A memory device comprising: (Lowe FIFO memory system 12) a First-in, First-out (FIFO) memory (Lowe FIFO memory system 12) where data is input and output; an address counter that controls writing and reading of the FIFO memory; (“FIFO buffers are implemented in RAM and the flow of data into and out of RAM is controlled by address counters” [Lowe col. 1 lines 22-23]. Wherein data flowing into and out of a FIFO buffer would be input and output data.) an address pointer generation circuit configured to check a status of the FIFO memory to compare a write clock domain and a read clock domain; and a flag generation circuit that compares the write clock domain and the read clock domain, and outputs the status of the FIFO memory based on a comparison of address pointers generated by the address pointer generation circuit, (“An integrated circuit having an embedded first-in, first-out ("FIFO") memory system uses an embedded block random access memory ("BRAM"). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.” [Lowe Abstract]. Wherein the addition of the offset to the pointer address is a generation of a new address pointer, making the binary adder an address pointer generator. Furthermore, checking if the two gray code values are equal is a comparison of address pointers. The conversion of the address pointers to gray code merely changes the representation of the address pointer’s value, so the gray code values are still address pointers during the comparison. Additionally, the address pointers being compared can be from read and write clock domains (Lowe claim 12 “reading a first pointer address … in a first clock domain; adding a first binary offset value to the first pointer address to produce a first sum; converting the first sum to a first gray code value; reading a second pointer address … in a second clock domain; converting the second pointer address to a second gray code value; comparing the first gray code value to a second gray code value; and, if the first gray code value equals the second gray code value; asserting a first comparator output”. The two clock domains depicted in Lowe Fig. 1 are a read clock and write clock). The logic block that produces a status flag is a flag generator, and the logic block produces the status flag based on the output of the comparison the gray code values (which are pointer addresses). Additionally, the logical components are noted to be circuits: “various embedded FIFO logic circuits, such as a write pointer 16, a read pointer 18, and status flag logic 20” [Lowe col. 3 lines 65-66]. The examiner also notes that in the claim limitation “configured to check a status of the FIFO memory to compare a write clock domain and a read clock domain”, “to compare …” is merely the intended use of the circuit configured to check a status of the FIFO memory.) wherein a write data width and a read data width are differently processed in the FIFO memory (a write data width and a read data width would inherently be processed differently in any FIFO memory because the FIFO memory would be storing a write data width’s amount of write data while the read data width would be used in memory accesses) wherein the address pointer generation circuit is further configured to: generate the address pointers in the unit of greatest common divisor of the write data width and the read data width (Applicant admitted prior art, “The related art asynchronous FIFO memory 200 has the same write data width and read data width, and includes address pointers 210w and 210r for comparing data between write and read clocks and a comparator. The unit of the address pointers corresponds to a data width since the read data width and the write data width are the same.” [specification of the instant application, page 2 lines 16-18]. The single data width would be the greatest common divisor of the read data width and the write data width).
Lowe does not appear to explicitly disclose wherein write data is processed in the write clock domain and read data is processed in the read clock domain, wherein the address pointer generation circuit is further configured to: increase a write address pointer by a first value by dividing the write data width by the greatest common divisor of the write data width and the read data width; and increase a read address pointer by a second value by dividing the read data width by the greatest common divisor.
However, Miller teaches wherein write data is processed in the write clock domain and read data is processed in the read clock domain (“the processing pipeline is engaged in the FIFO-load domain (clkA domain in this write-path example) or FIFO-unload domain (destination domain or clkB domain).” [Miller paragraph 22]. Wherein the unload domain would be a second clock domain in which read data is processed.)
Lowe and Miller are analogous art because they are from the same field of endeavor of FIFO memory.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lowe and Miller before him or her, to modify the apparatus of Lowe to include the attributes of wherein write data is processed in the write clock domain and read data is processed in the read clock domain of Miller because it will enhance apparatus efficiency.
The motivation for doing so would be that the asymmetries of Miller enable the use of error correcting codes with the FIFO memory, (“FIG. 3 illustrates an embodiment of a domain-cross FIFO memory 210 having a domain-dependent data width—operating with either a wider or narrower data width according to whether the processing pipeline is engaged in the FIFO-load domain (clkA domain in this write-path example) or FIFO-unload domain (destination domain or clkB domain). In the specific example shown, an ECC generator 211/213 implemented within processing stage Z produces an additional byte of output data for every four bytes of input data—in this case generating 8 bytes (8B) of ECC data in response 32 bytes (32B) of input data and thus expanding the width of the data supplied to downstream circuitry to 40 bytes (40B).” [Miller paragraph 22]) This would reduce error, thus enhancing efficiency.
Therefore, it would have been obvious to combine Lowe and Miller to obtain the invention as specified in the instant claim.
Neither Lowe nor Miller appear to explicitly disclose wherein the address pointer generation circuit is further configured to: increase a write address pointer by a first value by dividing the write data width by the greatest common divisor of the write data width and the read data width; and increase a read address pointer by a second value by dividing the read data width by the greatest common divisor.
However, Cheng teaches wherein the address pointer generation circuit is further configured to: increase a write address pointer by a first value by dividing the write data width by the greatest common divisor of the write data width and the read data width; and increase a read address pointer by a second value by dividing the read data width by the greatest common divisor (“To provide data rate adaptation, write counter 110 and read counter 120 increment their counts corresponding to their respective data widths. For example, if the write data width is 8 bits, write counter 110 increments WCOUNT in 8 bit increments such that WCOUNT counts as 0, 8, 16, 32, and so on. Similarly, if the read data width is 32 bits, read counter 120 increments RCOUNT in 32 bit increments such that RCOUNT counts as 0, 32, 64, 128, and so on. …Decoders … decode WCOUNT and RCOUNT to identify the current write address and current read address” [Cheng col. 3 line 66 – col. 4 line 17] Wherein the current write address and current read address would both be pointers. As the write and read addresses are derived from the write and read counters, increasing a counter would increase the respective address. Furthermore, increasing the pointers by a value obtained by dividing the corresponding data width by the greatest common divisor would have no effect on the asymmetric FIFO memory solution taught by Cheng, other than changing the units of the pointer address. As cited in the example above, Cheng increments counters that have units of bits by adding 8 and 32 to counters. The claimed invention would divide by 8, resulting in increasing counters that have units of 8 bits by 1 and 4, which is mathematically equivalent. This merely amounts to an arbitrary change in the digital representation of the pointer address; the pointer addresses themselves would be mathematically equivalent in both the apparatus of Cheng and in the claimed invention. Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art.).
Lowe/Miller and Chang are analogous art because they are from the same field of endeavor of FIFO memory.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lowe and Cheng before him or her, to modify the apparatus of Lowe to include the attributes of wherein the address pointer generation circuit is further configured to: increase a write address pointer by a first value by dividing the write data width by the greatest common divisor of the write data width and the read data width; and increase a read address pointer by a second value by dividing the read data width by the greatest common divisor of Cheng because it will enhance apparatus compatibility.
The motivation for doing so would be that with the programmable data ports of Cheng (“A first-in-first-out (FIFO) memory, comprising: an array of memory cells; a write address decoder coupled to the array, the write address decoder being configured to form a write port for the array having a programmable write port data width; a read address decoder coupled to the array, the read address decoder being configured to form a read port for the array having a programmable read port data width” [Cheng claim 1]), a programmer can easily modify the FIFO memory apparatus to meet the data width requirements of many different devices that a non-programmable FIFO memory apparatus would not be compatible with.
Therefore, it would have been obvious to combine Lowe and Cheng to obtain the invention as specified in the instant claim.
Regarding claim 2, Lowe/Miller/Cheng teaches The memory device of claim 1 wherein the FIFO memory comprises a first clock domain in which write data is processed and a second clock domain in which read data is processed, and is an asymmetric FIFO memory in which the write data width processed in the first clock domain and the read data width processed in the second clock domain are different from each other (“the processing pipeline is engaged in the FIFO-load domain (clkA domain in this write-path example) or FIFO-unload domain (destination domain or clkB domain).” [Miller paragraph 22]. Wherein the unload domain would be a second clock domain in which read data is processed.) and is an asymmetric FIFO memory in which the write data width processed in the first clock domain and the read data width processed in the second clock domain are different from each other (“FIG. 3 illustrates an embodiment of a domain-cross FIFO memory 210 having a domain-dependent data width—operating with either a wider or narrower data width according to whether the processing pipeline is engaged in the FIFO-load domain (clkA domain in this write-path example) or FIFO-unload domain (destination domain or clkB domain).” [Miller paragraph 22]).
Regarding claim 3, Lowe/Miller/Cheng teaches The memory device of claim 1 wherein the FIFO memory comprises a write address decoder and a read address decoder, the write address decoder is configured with the write data width, and the read address decoder is configured with the read data width (“A first-in-first-out (FIFO) memory, comprising: an array of memory cells; a write address decoder coupled to the array, the write address decoder being configured to form a write port for the array having a programmable write port data width; a read address decoder coupled to the array, the read address decoder being configured to form a read port for the array having a programmable read port data width” [Cheng claim 1]. Wherein programming the write and read ports with write and read data widths is synonymous with configuring the ports with the data widths).
Regarding claim 4, Lowe/Miller/Cheng teach The memory device of claim 1, wherein the address pointer generation circuit generates the address pointers in unit of greatest common divisor of the write data width and the read data width to compare address pointers between a first clock domain where write data is processed and a second clock domain where read data is processed (Applicant admitted prior art, “The related art asynchronous FIFO memory 200 has the same write data width and read data width, and includes address pointers 210w and 210r for comparing data between write and read clocks and a comparator. The unit of the address pointers corresponds to a data width since the read data width and the write data width are the same.” [specification of the instant application, page 2 lines 16-18]. The single data width would be the greatest common divisor of the read data width and the write data width. Miller also teaches a first clock domain where write data is processed and a second clock domain where read data is processed [see the rejection to claim 2 above]).
Regarding claim 5, Lowe/Miller/Cheng teach The memory device of claim 1, wherein the address counter counts a data width of each of a first clock domain where write data is processed and a second clock domain where read data is processed, which are included in the FIFO memory, (“To provide data rate adaptation, write counter 110 and read counter 120 increment their counts corresponding to their respective data widths. For example, if the write data width is 8 bits, write counter 110 increments WCOUNT in 8 bit increments such that WCOUNT counts as 0, 8, 16, 32, and so on. Similarly, if the read data width is 32 bits, read counter 120 increments RCOUNT in 32 bit increments such that RCOUNT counts as 0, 32, 64, 128, and so on.” [Cheng col. 3 line 66 – col. 4 line 17]) the address pointer generation circuit generates the address pointers in units of greatest common divisor of the write data width and the read data width to compare the address pointers between the first clock domain and the second clock domain, and (applicant admitted prior art, see the rejection to claim 4 above) the flag generation circuit comprises a comparator that compares the address pointer of the first clock domain with the address pointer of the second clock domain (“If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY)” [Lowe abstract]; see the rejection to claim 1 above).
Regarding claim 7, Lowe/Miller/Cheng teach The memory device of claim 5, wherein the flag generation circuit outputs a flag regarding the status of the FIFO memory based on a result of comparing the address pointer of the first clock domain with the address pointer of the second clock domain in the comparator (Lowe abstract and claim 12; see the rejection to claim 1 above).
Regarding claim 8, Lowe/Miller/Cheng teach The memory device of claim 5, wherein the address counter is driven in unit of the write data width and the read data width, and (“FIFO buffers are implemented in RAM and the flow of data into and out of RAM is controlled by address counters that track the read and write addresses being used” [Lowe col. 1 lines 22-24]. Wherein a person having ordinary skill in the art would recognize that a counter tracking the read and write addresses being used would entail incrementing the counter with the data widths of the writes and reads, as the amount of address space that is used by a data write or read corresponds to the width of the data being written or read. Furthermore, incrementing a counter by a value would be driving the counter with that value.) the address pointer generation circuit and the flag generation circuit are driven in the unit of the greatest common divisor of the write data width and the read data width (See applicant admitted prior art “The unit of the address pointers corresponds to a data width since the read data width and the write data width are the same.” [specification of the instant application, page 2 lines 17-18], wherein the singular data width is the greatest common divisor of the read data width and the write data width as they are the same. Since the unit of the address pointers is the greatest common divisor of the write data width and the read data width, driving the address pointer generator with that unit (to generate address pointers in that unit) would have been obvious. Furthermore, the flag generator uses the address pointers (see the rejections to claims 1 and 5 above), which would be in the unit of the greatest common divisor of the data widths, therefore it would also be driven in this unit).
Regarding claim 9, Lowe/Miller/Cheng teach The memory device of claim 1, wherein the write data width and the read data width are changed depending on settings (“A first-in-first-out (FIFO) memory, comprising: an array of memory cells; a write address decoder coupled to the array, the write address decoder being configured to form a write port for the array having a programmable write port data width; a read address decoder coupled to the array, the read address decoder being configured to form a read port for the array having a programmable read port data width” [Cheng claim 1]. Wherein programmable means a changeable setting).
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20050041450 A1 – Duh et al.
Relevant excerpt: “These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.” [abstract]
US 6681314 B1 – Matsuo et al.
Relevant excerpt: “A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N.times.k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.” [abstract]
US 7310396 B1 – Sabih
“An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into the shift register in synchronization with the output clock; input data is not loaded into the shift register on each cycle of the output clock, however, because the input clock is slower than the output clock. A clock comparison circuit compares the input and output clocks and tracks the history of data transfers into the shift register to determine whether a given input datum should be loaded into the shift register during a given period of the output clock. The clock comparison circuit writes input datum into the shift register periodically, skipping write cycles as necessary so that input and output data rates match.” [abstract]
Response to Arguments
The examiner thanks the applicant for their remarks of November 3, 2025. The remarks have been accepted and fully considered. However, some of the arguments are not persuasive.
In light of the amendments to the claims, specification, and drawings, all objections and 112(b) claim rejections indicated in the previous Office Action are withdrawn. However, the amendments to the claims introduce a new claim objection (see above).
On page 10 of applicant’s remarks, applicant recites “therefore, the present invention is distinct in that [in the prior art] different arbitrary numbers for the write data width and read data width are selected, whereas it is different from the [currently claimed] method of converting multiple units of the data width” (bracketed text added by the examiner for clarity, according to the examiner’s best interpretation and understanding of the applicant’s remarks. This interpretation is based on Cheng’s support for arbitrary numbers for the write data width and read data width (see the rejections to claims 3 and 5-9 above)).
The examiner notes that the prior art teaches devices that support different arbitrary numbers for the read and write data widths. As the choice of units to use is also arbitrary, the numbers after conversion would still be arbitrary (and thus supported by prior art devices and the choice to convert the units would also be an arbitrary, obvious design decision). Furthermore, unit conversion yields mathematically equivalent values, so the converted unit values of the instant application would be equivalent to the values taught by the prior art. The ultimate result of the conversion is a device with the same functionality as devices already contemplated by the prior art, and the choice to convert to a unit based on the greatest common divisor is merely an obvious choice between equivalents (selecting between two or more materials or processes is an obvious choice if their equivalence for the given purpose was known in the art when the invention was made. See MPEP 2144.06 II. Further, "[a]n express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious." Id., citing In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)). The claimed device’s composition including a structure for unit conversion is thus merely an arbitrary design choice without functional significance that would have been obvious to a person having ordinary skill in the art. Therefore the argument is not persuasive.
Also on page 10 of applicant’s remarks, applicant recites “In addition, the present invention is patentably different from the cited references in that data width conversion function is added to a conventional FIFO memory for clock conversion, thereby implementing a circuit with a smaller area than the prior art by using a clock conversion memory during data width conversion.”
The examiner disagrees that the addition of data width conversion is patentably different, as described above and in the claim rejections above. The examiner notes “a conventional FIFO memory for clock conversion” is applicant admitted prior art, as previously noted in the rejection to claim 4 (see above). The examiner notes that “using a clock conversion memory during data width conversion” is synonymous with “data width conversion function is added to a conventional FIFO memory for clock conversion”. The examiner also notes that the phrases “width conversion” and “clock conversion” are not recited in the claim language.
In response to applicant's argument that “thereby implementing a circuit with a smaller area than the prior art”, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
On pages 10-11 of applicant’s remarks, applicant recites “As articulated above, the present invention is distinct in that 1) a write address pointer is increased by a value obtained by dividing the write data width by the greatest common divisor of the write data width and the read data width, and the a read address pointer is increased by a value obtained by dividing the read data width by the greatest common divisor in original Claim 6.”
The claim language recited in this argument is no longer present in the claims after the amendments to the claims. Therefore the argument is moot. Additionally, see the updated claim rejections above.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The applicant generally summarizes the claim language or uses alternative language in their arguments rather than pointing out the specific relevant claim language.
On page 13 of applicant’s remarks, applicant recites “Applicant respectfully submits that the claims as presently amended are not anticipated by Lowe or rendered obvious by any combination with Cheng. Further, careful consideration of Miller, as mentioned above, adds nothing to deficiencies of either Lowe and/or Cheng, alone, or in any combination”.
This argument is not persuasive in light of the updated claim rejections and the examiner’s responses to arguments above. The examiner notes that it is unclear what “careful consideration of Miller, as mentioned above” is referring to as the applicant’s remarks do not appear to address the examiner’s application of Miller to the claim rejections.
The examiner additionally notes that the applicant’s argument is moot as it does not address the examiner’s application of applicant admitted prior art (as in the rejections to claims 4, 5, 8 of the previous and instant Office actions, of which at least one claim limitation to which the applicant admitted prior art was applied has been added via amendment to claim 1) or argue that the amended claims are patentably distinct from the applicant admitted prior art, whether individually or in combination.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN O’CONNELL whose telephone number is (571)270-7784. The examiner can normally be reached on Monday-Friday 9:30 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138