DETAILED ACTION
[1] Remarks
I. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claims 1-20 are pending and have been examined, where claims 1-6, 9-16 and 18-20 is/are rejected, claims 7, 17, and 20 is/are objected. Explanations will be provided below.
III. Inventor and/or assignee search were performed and determined no double patenting rejection(s) is/are necessary.
IV. Patent eligibility (updated in 2019) shown by the following: Claims 1-20 pass patent eligibility test because there is/are no limitation or a combination of limitations amounting to an abstract idea. Also, the following limitation or the combinations of the limitations: “activating, by the system controller, the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern; processing, by an image signal processor (ISP) in the SoC, the test pattern data to generate ISP test output data from the ISP; generating a checksum value of the ISP test output data; comparing the checksum value with a reference checksum value to verify a functionality of the ISP” effects a transformation or a reduction of a particular article to a different state or thing / adds a specific limitation(s) other than what is well-understood, routine and conventional in the field, or adding unconventional steps that confine the claim to a particular useful application and providing improvements to the technical field of system-on-chip verification, which recite additional elements that integrate the judicial exception into a practical application and amounting significant more.
[2] Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function. Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
Claim(s) 10-17 are not interpreted under 35 U.S.C. 112(f) or pre-AIA U.S.C. 112 6th paragraph because of the following reason(s): limitations are modified by sufficient structure or material for performing the claimed function.
Claim(s) 1-9 and 18-20 do not require 35 U.S.C. 112(f) or pre-AIA U.S.C. 112 6th paragraph interpretation because they are method claims and / or they are CRM claims.
Upon examination of the specification and claims, the examiner has determined, under the best understanding of the scope of the claim(s), rejection(s) under 35 U.S.C. 112(a)/(b) is not necessitated because of the following reasons: sufficient support are provided in the written description / drawings of the invention.
[3] Grounds of Rejection
Claim Rejections - 35 USC § 102
U.S.C. 102 Conditions for patentability; novelty.
[Editor Note: Applicable to any patent application subject to the first inventor to file provisions of the AIA (see 35 U.S.C. 100 (note) ). See 35 U.S.C. 102 (pre-AIA ) for the law otherwise applicable.]
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; or
(2) the claimed invention was described in a patent issued under section 151 , or in an application for patent published or deemed published under section 122(b) , in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
(b) EXCEPTIONS.—
(1) DISCLOSURES MADE 1 YEAR OR LESS BEFORE THE EFFECTIVE FILING DATE OF THE CLAIMED INVENTION.—A disclosure made 1 year or less before the effective filing date of a claimed invention shall not be prior art to the claimed invention under subsection (a)(1) if—
(A) the disclosure was made by the inventor or joint inventor or by another who obtained the subject matter disclosed directly or indirectly from the inventor or a joint inventor; or
(B) the subject matter disclosed had, before such disclosure, been publicly disclosed by the inventor or a joint inventor or another who obtained the subject matter disclosed directly or indirectly from the inventor or a joint inventor.
(2) DISCLOSURES APPEARING IN APPLICATIONS AND PATENTS.—A disclosure shall not be prior art to a claimed invention under subsection (a)(2) if—
(A) the subject matter disclosed was obtained directly or indirectly from the inventor or a joint inventor;
(B) the subject matter disclosed had, before such subject matter was effectively filed under subsection (a)(2), been publicly disclosed by the inventor or a joint inventor or another who obtained the subject matter disclosed directly or indirectly from the inventor or a joint inventor; or
(C) the subject matter disclosed and the claimed invention, not later than the effective filing date of the claimed invention, were owned by the same person or subject to an obligation of assignment to the same person.
Claims 18-19 are rejected under 35 U.S.C. 102(b)(1) as being anticipated by LIM (US 20160295205).
Regarding claim 18, LIM discloses a method for controlling a functional safety image signal processor comprising:
generating an image signal processor (ISP) test pattern by modulating a plurality of pseudo random number values with a corresponding plurality of values from an edge pattern that includes edge structures (see figure 5, 501 reads on producing test pattern and 503 route test pattern through selected test and image processing stages to produce test pattern output result, also see paragraph 56, Multiple noise types such as row noise, column noise, area noise, fixed pattern noise, pseudo-random noise, random noise, and generally any type of noise can be generated by noise generator 425);
supplying the ISP test pattern to an ISP pipeline as input image data which is processed by the ISP pipeline to output ISP test output data (see figure 3, shows the pipeline);
generating a checksum of the ISP test output data (see figure 3, 211 checksum generator); and
comparing the checksum with a previously generated checksum (see paragraph 51, Checksum generator 211 may output an error flag if the checksum it generates for the received data corresponding to a known test pattern that has passed through a known subset of image processing blocks in the processing blocks).
Regarding claim 19, LIM discloses the method of claim 18, wherein the checksum is compared with the previously generated checksum to verify a functionality of the functional safety image signal processor (see paragraph 51, Checksum generator 211 may output an error flag if the checksum it generates for the received data corresponding to a known test pattern that has passed through a known subset of image processing blocks in the processing blocks, paragraph 71, control circuitry 17 may assert an error signal and/or notify the user if the checksums do not match, in response to an output result checksum not matching an expected test pattern output checksum, circuitry 17 may assert an error flag/signal that alerts a processing controller in storage and processing circuit 16/24 or the user of system 900).
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIM (US 20160295205) in view of Maeno (US 20060236112).
Regarding claim 1, LIM discloses a method for verifying functional safety of an image signal processor, comprising:
configuring, by a system controller in a system-on-chip (SoC), one or more edge pattern settings in a test pattern generator (see figure 1, imaging system on chip and figure 3, 197 test pattern generator);
processing, by an image signal processor (ISP) in the SoC, the test pattern data to generate ISP test output data from the ISP (see figure 5, 501 reads on producing test pattern and 503 route test pattern through selected test and image processing stages to produce test pattern output result, also see paragraph 56, Multiple noise types such as row noise, column noise, area noise, fixed pattern noise, pseudo-random noise, random noise, and generally any type of noise can be generated by noise generator 425);
generating a checksum value of the ISP test output data (see figure 3, 211 checksum generator);
comparing the checksum value with a reference checksum value to verify a functionality of the ISP (see paragraph 51, Checksum generator 211 may output an error flag if the checksum it generates for the received data corresponding to a known test pattern that has passed through a known subset of image processing blocks in the processing blocks); and
reporting an error in response to a difference between the checksum value and the reference checksum value (see figure 5, 509 and paragraph 71, control circuitry 17 may assert an error signal and/or notify the user if the checksums do not match, in response to an output result checksum not matching an expected test pattern output checksum, circuitry 17 may assert an error flag/signal that alerts a processing controller in storage and processing circuit 16/24 or the user of system 900).
LIM is silent in disclosing activating, by the system controller, the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern.
Maeno discloses the method of claim 18, wherein generating the ISP test pattern comprises:
activating, by the system controller, the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern (see figure 12, multiplication is read as modulation, where the document image is read as test pattern, the watermark image is read as PN code):
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include activating, by the system controller, the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern in order to allow engineers to test image sensors to their limits by checking for artifacts, aliasing, or edge-blurring effects, improving image acquisition.
Regarding claim 2, Maeno discloses the method of claim 1, where activating the test pattern generator to generate test pattern data comprises providing an input seed value to a pseudo random number generator to generate the sequence of pseudo random number values (see figure 30, illustration below):
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See the motivation for claim 1. Also, an initial seed guarantees you can reproduce the same sequence of numbers, which can reproduce results to be verify by another user.
Regarding claim 3, Maeno discloses the method of claim 2, where activating the test pattern generator to generate test pattern data comprises generating or obtaining the edge pattern comprising a plurality of defined values arranged in the edge pattern to define edge structures (see figure 29 illustration below):
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See the motivation for claim 1. Also it converts raw image matrices into boundaries, such as object outlines or contrast discontinuities, which are necessary for object recognition and segmentation.
Regarding claim 4, Maeno discloses the method of claim 3, where activating the test pattern generator to generate test pattern data comprises applied the sequence of values from the edge pattern as per-pixel scaling factors to modulate the sequence of pseudo random numbers (see figure 12, the sequence in the watermark image includes white, gray and dark pixel scaling values):
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See the motivation for claims 1. Also, including scaling factors randomize further more to
prevents attackers from deducing the seed of a pseudo-random number generator and allowing users to reproduce the same results for reproducibly.
Regarding claim 5, Maeno discloses the method of claim 4, where the system controller activates the test pattern generator to generate test pattern data during at least one synchronization phase of an image raster scan process (see figure 27, where the top profile is in synchronize with the image below):
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See the motivations for claims 3 and 4.
Regarding claim 6, LIM discloses the method of claim 1, where the functionality of the ISP meets at least a subset of integrity requirements of an Automotive Safety Integrity Level protocol (see paragraph 50, Checksum generator 211 may generate a checksum for the data output from additional image processing blocks or second ASIL check block 207, where ASIL is Automotive Safety Integrity Level).
3. Claims 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIM (US 20160295205) in view of Maeno (US 20060236112) and Hsuan (US 20120057703).
Regarding claim 8, the combination of LIM and Maeno as a whole discloses all the limitations of claim 1 but is silent in disclosing the method of claim 1, where the system controller accesses a table comprising at least a first input seed value and corresponding reference checksum value. Hsuan discloses the method of claim 1, where the system controller accesses a table comprising at least a first input seed value and corresponding reference checksum value (see paragraph 33, the pixel buffer 102 may maintain multiple sets of fiducial data 114, each set of fiducial data corresponding to a reference checksum 116 (e.g., a current set of fiducial data used for a particular source image 110 will also be associated with a current reference checksum maintained by the image transformation monitor 104)).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include comparing a newly generated checksum against a known reference, the system can instantly detect memory corruption, hardware faults, or unauthorized modifications, which improves security.
Regarding claim 9, Hsuan discloses the method of claim 1, where the system controller accesses a table comprising a first pseudo random number seed value, a first set of edge generator settings for generating the edge pattern, and a corresponding a corresponding reference checksum value (see citation in claim 8, also see paragraph 22, In the event of a match between the unmasked CRC checksum and the reference CRC value, terminal specific de-randomizer 310 is to use a seed value to generate a random sequence and use it de-randomize one or more IEs using an inverse randomizer scheme as that of terminal specific randomizer 252). See the motivation for claim 8. Also, it provides a starting point to generate a sequence of pseudo-random numbers and by using the same seed, the system can reproduce the exact same pattern every time improving reproducibly.
3. Claims 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIM (US 20160295205) in view of Hsuan (US 20120057703) and Maeno (US 20060236112).
Regarding claim 10, LIM discloses a system-on-chip (SoC) apparatus comprising:
an image signal processor (ISP) pipeline that is connected and configure to receive and process input image data and to generate output image data (see figure 1, show a pipeline from top to bottom, where the top is the image pixel array which is connect and configured to receive and process);
a checksum generator configured to generate a checksum value from the output image data (see figure 3, 211 is read as the checksum generator, where the output image is the output of 209);
supply the test pattern data to the ISP pipeline as input image data which is processed by the ISP pipeline to output the output image data as ISP test output data (see figure 3, 197 a test pattern is supplied by the test pattern generator);
receive a checksum value generated from the ISP test output data by the checksum generator (see figure 3, 211 receives check sum value from 209); and
compare the checksum value with the reference checksum value to verify a functionality of the ISP pipeline (see paragraph 51, Checksum generator 211 may output an error flag if the checksum it generates for the received data corresponding to a known test pattern that has passed through a known subset of image processing blocks in the processing blocks).
LIM is silent in disclose a processing circuit that configures a configuration memory table with the one or more configurable edge pattern settings and corresponding input seed value and reference checksum value.
Hsuan discloses a processing circuit that configures a configuration memory table with the one or more configurable edge pattern settings and corresponding input seed value and reference checksum value (see paragraph 33, the pixel buffer 102 may maintain multiple sets of fiducial data 114, each set of fiducial data corresponding to a reference checksum 116, e.g., a current set of fiducial data used for a particular source image 110 will also be associated with a current reference checksum maintained by the image transformation monitor 104)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include comparing a newly generated checksum against a known reference, the system can instantly detect memory corruption, hardware faults, or unauthorized modifications.
Hsuan is silent in disclosing activate a test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern.
Maeno discloses activate a test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern (see figure 12, multiplication is read as modulation, where the document image is read as test pattern, the watermark image is read as PN code):
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include activating, by the system controller, the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern in order to allow engineers to test image sensors to their limits by checking for artifacts, aliasing, or edge-blurring effects, improving image acquisition.
Regarding claim 11, LIM discloses the SoC apparatus of claim 10, where the processing circuit is further configured to report an error in response to a difference between the checksum value and the reference checksum value (see paragraph 71, at step 509, control circuitry 17 may assert an error signal and/or notify the user if the checksums do not match, in response to an output result checksum not matching an expected test pattern output checksum, circuitry 17 may assert an error flag/signal that alerts a processing controller).
Regarding claim 12, Maeno discloses the SoC apparatus of claim 10, where the test pattern generator comprises a pseudo random number generator (see figure 29, illustration below, the PN code is read as Pseudo random Number input image (1)):
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See the motivation for claim 11.
Regarding claim 13, Maeno discloses the SoC apparatus of claim 12, where the processing circuit is configured to provide the input seed value to the pseudo random number generator to generate the sequence of pseudo random number values (see figure 30, illustration below).
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See the motivation for claim 1. Also, an initial seed guarantees you can reproduce the same sequence of numbers, which can reproduce results to be verify by another user and allowing users to reproduce the same results for reproducibly.
Regarding claim 14, Maeno discloses the SoC apparatus of claim 13, where the test pattern generator is configured to generate or obtain the edge pattern comprising a plurality of defined values arranged in the edge pattern to define linear edge structures (see figure 29 illustration below):
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See the motivation for claim 10. Also, the alignment of linear edges is used to measure or test systems allows engineers to analyze blur, determine measure system sharpness and evaluate geometric distortion.
Regarding claim 15, Maeno discloses the SoC apparatus of claim 14, where the test pattern generator is configured to apply sequence of values from the edge pattern as per-pixel scaling factors to modulate the sequence of pseudo random numbers (see figure 12, where the bright, gray and dark pixels are read as pixels that scales the document image):
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See the motivation for claim 10. Also modulating pseudorandom numbers using a structural edge pattern hide fixed-pattern noise and generate spatially varying textures for device testing, which prevents misaligning with physical pixels.
Regarding claim 16, LIM discloses the SoC apparatus of claim 10, where the functionality of the ISP pipeline meets at least a subset of the integrity requirements of an Automotive Safety Integrity Level protocol (see paragraph 50, Checksum generator 211 may generate a checksum for the data output from additional image processing blocks or second ASIL check block 207, where ASIL is Automotive Safety Integrity Level).
[4] Claim Objections
Claim(s) 7, 17 and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the examiner cannot find any applicable prior art teaching the following: the method of claim 1, where configuring one or more edge pattern settings in the test pattern generator comprises configuring one or more overflow values in a pixel clock counter to generate an overflow signal which triggers a selection circuit to switch between at least first and second output values when generating the edge pattern; in combination with the rest of the limitations of claim 1.
Kitano (US 20120092542) discloses the output number of dot clocks (TDH_MAX/Tdd1) exceeds the maximum value Cdd_MAX, the display control section 30b assumes that an overflow is likely to occur and switches the cycle of the dot clocks DDotclock to cycle Tdd2. As a result, overflow of the counter 41 can be avoided (see paragraph 55), but does not disclose the method of claim 1, where configuring one or more edge pattern settings in the test pattern generator comprises configuring one or more overflow values in a pixel clock counter to generate an overflow signal which triggers a selection circuit to switch between at least first and second output values when generating the edge pattern.
Regarding claim 20, the examiner cannot find any applicable prior art teaching the following: the method of claim 18, wherein generating the ISP test pattern comprises: providing an input seed value to a pseudo random number generator to generate the plurality of pseudo random number values; generating the edge pattern by counting pixel clock pulses with a pixel clock counter having an overflow value to generate an overflow signal whenever the pixel clock counter reaches the overflow value, thereby triggering a selection circuit to switch between first and second output values when generating the plurality of values for the edge pattern; and applied the plurality of values from the edge pattern as per-pixel scaling factors to modulate the plurality of pseudo random number values; in combination with the rest of the limitations of claim 1.
Regarding claim 17 see the rationale for claim 20.
Maeno (US 20060236112) discloses the method of claim 18, wherein generating the ISP test pattern comprises:
providing an input seed value to a pseudo random number generator to generate the plurality of pseudo random number values (see figure 30, PN codes are generated);
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applied the plurality of values from the edge pattern as per-pixel scaling factors to modulate the plurality of pseudo random number values (see figure 12, multiplication is read as modulation):
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Maeno discloses scrolling the Filter A, and counting F (A) according to the unit image U (x, y) at the same time, so as to obtain a maximal value, where the maximal value of F (A) is taken as an output value of the unit image U (x, y) from the Filter A and denoted with Fu (A, x, y) (see paragraph 143), but is silent in disclosing generating the edge pattern by counting pixel clock pulses with a pixel clock counter having an overflow value to generate an overflow signal whenever the pixel clock counter reaches the overflow value, thereby triggering a selection circuit to switch between first and second output values when generating the plurality of values for the edge pattern.
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEX LIEW (duty station is located in New York City) whose telephone number is (571)272-8623 (FAX 571-273-8623), cell (917)763-1192 or email alexa.liew@uspto.gov. Please note the examiner cannot reply through email unless an internet communication authorization is provided by the applicant. The examiner can be reached anytime.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MISTRY ONEAL R, can be reached on (313)446-4912. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEX KOK S LIEW/Primary Examiner, Art Unit 2674 Telephone: 571-272-8623
Date: 7/4/26
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