Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The objections to the specification are withdrawn, due to the amendment dated 03/30/2026, which replaces the title of the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha, US PGPub 2016/0276033.
With respect to claim 1, Cha teaches a memory device, comprising:
a memory cell array (par. 22 and fig. 1, nonvolatile memory device 200), including:
at least one first memory block (par. 24 and fig. 1, test result storage unit 214); and
a plurality of second memory blocks (par. 27 and fig. 1, the plurality of memory blocks BLK0 to BLKj), wherein part of the plurality of second memory blocks are configured as sampling memory blocks (par. 23 and fig. 1, sample memory blocks BLK_SP); and
a peripheral circuit coupled with the memory cell array (par. 23 and fig. 1, test device 100) and configured to:
perform an erase operation on the sampling memory blocks (pars. 50-51 and fig. 1, an erase operation is performed on a target memory block among sample blocks); and
record an erase count of the sampling memory blocks in the at least one first memory block (par. 57 the test result based on the pass erase loop count is stored. Par. 63 discloses that the test result stored may be the current pass erase loop count itself).
With respect to claim 2, Cha teaches the memory device of claim 1, wherein the erase operation is a first erase operation, the erase count is a first erase count, and the peripheral circuit is configured to:
perform a second erase operation on a selected second memory block (par. 58 and fig. 5, it is determined if all sample memory blocks are erased, and if not, the procedure is performed for the next sample memory block); and
record, based on the selected second memory block belonging to the sampling memory blocks, a second erase count of the selected second memory block in the at least one first memory block (pars. 57 and 63, the erase loop count is stored as the test result).
With respect to claim 14, Cha teaches an operation method of a memory device, comprising:
performing an erase operation on a sampling memory block of a memory cell array of the memory device, the memory cell array including at least one first memory block and a plurality of second memory blocks, part of the plurality of second memory blocks configured as sampling memory blocks (pars. 50-51 and fig. 1, an erase operation is performed on a target memory block among sample blocks); and
recording an erase count of the sampling memory block in at least one first memory block (par. 57 the test result based on the pass erase loop count is stored. Par. 63 discloses that the test result stored may be the current pass erase loop count itself).
With respect to claim 15, Cha teaches the operation method of claim 14, whereing the erase operation is a first erase operation, the erase count is a first erase count, and the method further includes:
performing a second erase operation on a selected second memory block (par. 58 and fig. 5, it is determined if all sample memory blocks are erased, and if not, the procedure is performed for the next sample memory block); and
recording, based on the selected second memory block belonging to the sampling memory block, a second erase count of the selected second memory block in the at least one first memory block (pars. 57 and 63, the erase loop count is stored as the test result).
With respect to claim 16, Cha teaches the operation method of claim 14, further including:
in response to the erase operation performed on the sampling memory block being an initial erase operation in a current power supply cycle of the memory device, searching a physical page group corresponding to the sampling memory block for a physical page recording a largest erase count of a plurality of erase counts of the sampling memory block (This is a contingent limitation based on the condition “the erase operation performed on the sampling memory block being a first erase operation in a current power supply cycle of the memory device,” and is not required to occur); and
storing address information of the physical page recording the largest erase count of the plurality of erase counts of the sampling memory block in a first region of a register (This limitation is based on the previous contingent limitation and is not required to occur).
With respect to claim 17, Cha teaches the operation method of claim 16, wherein searching the physical page group corresponding to the sampling memory block for the physical page recording the largest erase count of the sampling memory block includes searching the physical page group corresponding to the sampling memory block for the physical page recording the largest erase count of the plurality of erase counts of the sampling memory block by using dichotomy (This limitation is based on a prior contingent limitation and is not required to occur).
With respect to claim 18, Cha teaches the operation method of claim 14, further including, in response to the erase operation performed on the sampling memory block being an Nth erase operation in a current power supply cycle of the memory device, reading address information of a physical page recording the largest erase count of a plurality of erase counts of the sampling memory block that is stored in a first region of a register, wherein N is an integer greater than or equal to 2 (This is a contingent limitation based on the condition “the erase operation performed on the sampling memory block being an Nth erase operation in a current power supply cycle of the memory device,” and is not required to occur).
With respect to claim 19, Cha teaches the operation method of claim 16, further including, determining, based on identifier information stored in a second region of the register, whether the erase operation performed on the sampling memory block is the intial erase operation in the current power supply cycle (This is a contingent limitation based on the condition “identifier information stored in a second region of the register,” and also based on a prior contingent limitation, and is not required to occur).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha, as applied to claim 1 above, in view of Lee, US PGPub 2020/0097399.
With respect to claim 11, Cha teaches all limitations of the parent claim, but fails to teach wherein the memory cell array includes a plurality of memory planes, a memory plane includes one of the plurality of second memory blocks, and all the sampling memory blocks belong to a same memory plane. Lee further teaches the memory device of claim 1, wherein the memory cell array includes the one of the plurality of memory planes, a memory plane includes one of the plurality of second memory blocks, and all the sampling memory blocks belong to a same memory plane (par. 39, a plurality of planes, each including a plurality of memory blocks 152 to 156, corresponding to the sampling memory blocks).
It would have been obvious to one of ordinary skill in the art, having the teachings of Cha and Lee before him before the earliest effective filing date, to modify the memory device of Cha with the memory device of Lee, in order to have larger storage space in a nonvolatile memory, as taught by Lee in par. 53.
With respect to claim 12, Cha and Lee teach all limitations of the parent claim. Cha further teaches the memory device of claim 11, wherein the one of the plurality of second memory blocks in the memory plane are numbered in sequence, and a same number difference exists between adjacent sampling memory blocks (pars. 23, 27 and fig. 1, the memory blocks are numbered in sequence, BLK0 to BLKi for the sampling memory blocks, followed by BLKi+1 to BLKj of the remaining memory blocks).
With respect to claim 13, Cha teaches all limitations of the parent claim, but fails to teach wherein each one of the plurality of second memory blocks includes first memory cells, and each of the first memory cells can store at least one bit of data; and the first memory block includes second memory cells, and each of the second memory cells can store one bit of data. Lee further teaches the memory device of claim 1, wherein the second memory block includes first memory cells, and each of the first memory cells can store at least one bit of data; and the first memory block includes second memory cells, and each of the second memory cells can store one bit of data (par. 53, each of BLOCK0 to BLOCKN-1 may store 1-bit data or a multi-level cell storing 2- or more bit data.).
It would have been obvious to one of ordinary skill in the art, having the teachings of Cha and Lee before him before the earliest effective filing date, to modify the memory device of Cha with the memory device of Lee, in order to have larger storage space in a nonvolatile memory, as taught by Lee in par. 53.
With respect to claim 20, Cha teaches a memory system, comprising:
a memory device (par. 22 and fig. 1, test system 10), including:
a memory cell array (par. 22 and fig. 1, nonvolatile memory device 200), including:
at least one first memory block (par. 24 and fig. 1, test result storage unit 214); and
a plurality of second memory blocks (par. 27 and fig. 1, the plurality of memory blocks BLK0 to BLKj), wherein part of the plurality of second memory blocks are configured as sampling memory blocks (par. 23 and fig. 1, sample memory blocks BLK_SP); and
a peripheral circuit coupled with the memory cell array (par. 23 and fig. 1, test device 100) and configured to:
perform an erase operation on the sampling memory blocks (pars. 50-51 and fig. 1, an erase operation is performed on a target memory block among sample blocks); and record an erase count of the sampling memory blocks in the at least one first memory block (par. 57 the test result based on the pass erase loop count is stored. Par. 63 discloses that the test result stored may be the current pass erase loop count itself); and
Cha fails to teach a wear leveling function. Lee teaches:
a memory controller having a wear leveling function and coupled with the memory device (par. 42 and fig. 1, the controller 130 includes a wear-leveling operation module 506).
It would have been obvious to one of ordinary skill in the art, having the teachings of Cha and Lee before him before the earliest effective filing date, to modify the memory device of Cha with the memory device of Lee, in order to keep wear levels of memory blocks included in the memory device uniform thereby increasing the lifetime of the flash memory, as taught by Lee in par. 63.
Allowable Subject Matter
Claims 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for the indication of allowable subject matter are included in the Office Action dated 12/30/2025.
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive. Applicant’s arguments on pages 10-17, with respect to independent claim 1, are directed towards Cha allegedly failing to teach to “record an erase count of the sampling memory blocks in the at least one first memory block. In doing so, Applicant is mapping element 420 of fig. 6 as the memory cell array that contains the first block. This is in contrast to the outstanding rejection, that maps nonvolatile memory device 400 to the memory cell array of the claim. Test result storage unit 414 is part of the nonvolatile memory device 400, and thus constitutes a first memory block of the memory cell array. The arguments regarding independent claims 14 and 20 are similar to the arguments regarding claim 1, and are unpersuasive for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art is replete with examples of storing an erase count in a first memory block of a memory cell array. See, for example, Hung et al., US PGPub 2023/0015202, claim 20, and Shin et al., US PGPub 2021/0365202.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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