DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant communication is in response to communication filed on 08/23/2024.
Claims 1-21 are pending of which claims 1, 8, and 16 are independent.
Internet Communications
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 16-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schemmann et al (US 20230403128 A1, here in after referred to as D1) in view of Bowler et al (US 20260072583 A1).
Regarding claim 1, D1 discloses a method (i.e. Figs. 1-3) comprising: receiving, from at least one of a node (Fig. 1A, 2A, 2B FDX Node 102) or an upstream amplifier (Fig. 2A and 2B FDX Amplifier 104 and Fig. 3 FDX amplifier 302) , a downstream signal, wherein the first FDX amplifier is configured to modulate the downstream signal via at least one of the gain and the equalization associated with the one or more downstream signals; (See Fig. 2B first FDX amplifier 104 receives downstream signal from FDX node 102 and modulates the downstream signal through gain 314 of Fig. 3 – see at least paragraphs 22 and 31)
sending, to a second FDX amplifier downstream of the first FDX amplifier, the modulated downstream signal; (See Fig. 2B the modulated downstream signal is sent to the second FDX amplifier 104 connected to the first FDX amplifier 104 via tap 112-4)
receiving, from the second FDX amplifier, an upstream signal, wherein the first FDX amplifier is configured to modulate the upstream signal via at least one of the gain and the equalization associated with the one or more upstream signals; (From second FDX amplifier 104 an upstream signal modulated through gain 330 of Fig. 3 is sent in upstream direction to the first FDX amplifier 104 through tap 112-4. See paragraphs 23, 33, and 34) and
sending, to the at least one of the node or the upstream amplifier, the modulated upstream signal. (See Fig. 2B the modulated upstream signal is sent to the first FDX amplifier 104 and FDX node 102 connected to the second FDX amplifier 104 via tap 112-4. See paragraphs 22-23 and 31-34)
D1 fails to disclose configuring, via a configuration system associated with a first full duplex DOCSIS (FDX) amplifier, at least one of a gain and an equalization associated with one or more downstream signals received by the first FDX amplifier; and configuring, via the configuration system associated with the first FDX amplifier, at least one of a gain and an equalization associated with one or more upstream signals received by the first FDX amplifier.
Bowler discloses, in the same endeavor, FDX amplifier for extended spectrum DOCSIS.
Bowler further discloses configuring, via a configuration system associated with a first full duplex DOCSIS (FDX) amplifier (Fig. 1 system 10 with FDX amp 14 and paragraph 7), at least one of a gain and an equalization associated with one or more downstream signals received by the first FDX amplifier (Fig. 6 FDX AMP 100 paragraphs33-34, 38, and 44-45 at least one of a gain and an equalization associated with one or more downstream signals is configured. Note also in paragraph 42 that FDX AMP 100 modulates the gain so that the modulated output of the amplifier is what is needed to provide unity gain, given the adjacent span.); and configuring, via the configuration system associated with the first FDX amplifier, at least one of a gain and an equalization associated with one or more upstream signals received by the first FDX amplifier. (Fig. 6 FDX AMP 100 paragraphs 52-53 and 56-57 at least one of a gain and an equalization associated with one or more upstream signals is configured. Note also in paragraph 42 that FDX AMP 100 modulates the gain so that the modulated output of the amplifier is what is needed to provide unity gain, given the adjacent span.)
In view of the above, having D1’s FDX amplifier and then given the well- established teaching of Bowler’s techniques for configuring gain and equalization, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify D1’s FDX amplifier as taught by Bowler’s techniques for configuring gain and equalization, since Bowler states in paragraph 10 that the modification results in an improved system for amplification of signals to reduce noise or other degradations in the signal being amplified.
Regarding claim 16, D1 discloses a method comprising:
(Fig. 2B FDX Amplifier 104 between tap 112-1 and tap 112-4), at least one of an equalization or a gain associated with correcting at least one of a distortion or attenuation of a received signal, wherein the received signal comprises at least one of a downstream signal or an upstream signal; (See Fig. 2B first FDX amplifier 104 receives downstream signal from FDX node 102 and modulates the downstream signal through gain 314 of Fig. 3 – see at least paragraphs 22 and 31. From second FDX amplifier 104 an upstream signal modulated through gain 330 of Fig. 3 is sent in upstream direction to the first FDX amplifier 104 through tap 112-4. See paragraphs 23, 33, and 34) correcting, via the configured at least one equalization or gain, the received signal(Fig. 3 gain 330 and Fig. 3 314 provide the correction of the received signal); and causing sending the corrected received signal, wherein downstream signals are sent to a downstream FDX amplifier, and wherein upstream signals are sent to at least one of an upstream FDX amplifier or an upstream FDX node. (See Fig. 2B the modulated upstream signal is sent to the first FDX amplifier 104 and FDX node 102 connected to the second FDX amplifier 104 via tap 112-4. See paragraphs 22-23 and 31-34 and See Fig. 2B the modulated downstream signal is sent to the second FDX amplifier 104 connected to the first FDX amplifier 104 via tap 112-4)
D1 fails to disclose configuring, via a configuration system associated with a first full duplex DOCSIS (FDX) amplifier at least one of an equalization or a gain associated with correcting at least one of a distortion or attenuation of a received signal.
Bowler in the same endeavor, discloses configuring, via a configuration system associated with a first full duplex DOCSIS (FDX) amplifier at least one of an equalization or a gain associated with correcting at least one of a distortion or attenuation of a received signal. (Fig. 6 FDX AMP 100 paragraphs33-34, 38, and 44-45 at least one of a gain and an equalization associated with one or more downstream signals is configured. (Fig. 6 FDX AMP 100 paragraphs 52-53 and 56-57 at least one of a gain and an equalization associated with one or more upstream signals is configured. Note also in paragraph 42 that FDX AMP 100 modulates the gain so that the modulated output of the amplifier is what is needed to provide unity gain, given the adjacent span.)
In view of the above, having D1’s FDX amplifier and then given the well- established teaching of Bowler’s techniques for configuring gain and equalization, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify D1’s FDX amplifier as taught by Bowler’s techniques for configuring gain and equalization, since Bowler states in paragraph 10 that the modification results in an improved system for amplification of signals to reduce noise or other degradations in the signal being amplified.
Regarding claim 2, D1 modified by Bowler discloses the method of claim 1, D1 further discloses wherein modulating the upstream signal via the at least one of the gain and the equalization further comprises reducing, via an echo canceler, an echo of the downstream signal. (Per paragraphs 30 and 31 D1 discloses the gain and equalization comprises an echo canceler)
Regarding claim 3, D1 modified by Bowler discloses the method of claim 2, D1 further disclose wherein the echo of the downstream signal comprises a reflection of the downstream signal in the upstream signal. (Per paragraphs 30 and 31 D1 discloses the gain and equalization comprises an echo canceler)
Regarding claim 4, D1 modified by Bowler discloses the method of claim 1, D1 further discloses wherein the configuration system comprises a system on chip component of the first FDX amplifier. (i.e. D1 Fig. 3 is system on chip)
Regarding claim 5, D1 modified by Bowler discloses the method of claim 1, D1 further discloses wherein the configuration system digitizes analog signals from the FDX amplifier via an analog to digital converter, and wherein the configuration system outputs, to the FDX amplifier, analog signals via a digital to analog converter. (See paragraphs 4, 18, 20, 21-25 on analog to digital converter and digital to analog converter in the paths of the FDX amplifier)
Regarding claim 6, D1 modified by Bowler discloses the method of claim 1, D1 further discloses, wherein the downstream signal and the upstream signal occupy at least partially overlapping portions of a frequency band. (See Paragraph 33 and abstract of D1 where upstream and downstream share same frequency in full duplex operation such as FDX)
Regarding claim 7, D1 modified by Bowler discloses the method of claim 6, D1 further discloses, wherein the downstream signal occupies at least a portion of the frequency band from substantially 100 megahertz to substantially 1.2 gigahertz, and wherein the upstream signal occupies at least a portion of the frequency band from substantially 8 megahertz to 700 megahertz. (See D1 paragraph 16 upstream 5-85 MHZ and downstream 108-834 MHZ of full bandwidth of 1.28 GHZ in paragraph 31)
Regarding claim 17, D1 modified by Bowler discloses the method of claim 6, D1
The method of claim 16, wherein the downstream FDX amplifier is configured to apply a
further correction to the downstream signal based on at least one of a distortion or an attenuation associated with the sending the signal from the first FDX amplifier to the downstream FDX amplifier. (See D1 Fig. 3 gain/attenuator 330 and 314 doing correction in upstream and downstream direction.)
Regarding claim 18, claim 18 is rejected in the same scope as claim 5.
Regarding claim 19, claim 19 is rejected in the same scope as claim 2.
Regarding claim 20, claim 18 is rejected in the same scope as claim 6.
Regarding claim 21, claim 18 is rejected in the same scope as claim 7.
Allowable Subject Matter
Claims 8-15 are allowed.
Conclusion
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/HABTE MERED/Primary Examiner, Art Unit 2474
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