Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim(s) 1-6, 8-13, 15-19, 21 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims fall within at least one of the four categories of patent eligible subject matter. However, the claimed invention is directed to performing steps that fall within the mental process groupings of abstract ideas because they cover concepts performed in the human mind. An analysis of the claims regarding subject matter eligibility follows:
Step1: Claim(s) 1-6, 8-13, 15-19, 21 recite an apparatus, a medium, and a method, therefore satisfying Step 1 of the analysis.
Step 2A, Prong 1: Claim(s) 1, 9, 16 recite identifying a fault condition of the memory system associated with performing the operation in response to receiving the command, which, under their broadest reasonable interpretation, covers performance of the limitations entirely in the human mind and/or with the aid of pen and paper. Specifically, the step of identifying a fault condition may be practically performed in the human mind using observation, evaluation, and judgement of memory system (MPEP 2106.04(a)(2), subsection Ill). For example, “identifying” in the context of the claim(s) encompasses a user identifying a fault condition of the memory system associated with performing the operation in response to receiving the command.
Claim(s) 2-6, 8, 10-13, 15, 17-19, 21 recite further limitations that fall under the judicial exception as recited in claim(s) 1, 9, 16. Each of the further limitations encompass performance of the steps within the human mind.
Step 2A, Prong 2: The additional elements recited in claim(s) 1, 9, 16, “a memory”, “memory arrays,” “circuitry,” “medium,” “processor,” “receiving a command to perform an operation on one or more memory arrays of the memory system;” and “transmitting a message that indicates the fault condition in accordance with identifying the fault condition,” do not integrate the judicial exception into a practical application. These limitations are directed to implementing the abstract idea using generic computer components (MPEP 2106.05(f)) and recite mere data gathering and outputting recited at a high level of generality, and thus are insignificant extra-solution activity (MPEP 2106.05(g)).
Claim(s) 2-6, 8, 10-13, 15, 17-19, 21 recite further details regarding generating a code, generating the message, and receiving a notification. These claims contain no additional elements which would integrate the abstract idea into a practical application.
Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the identified abstract idea.
Step 2B: Claim(s) 1, 9, 16 do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed in Step 2A, Prong 2 above, the recitations of “a memory”, “memory arrays,” “circuitry,” “medium,” “processor,” “receiving a command to perform an operation on one or more memory arrays of the memory system;” and “transmitting a message that indicates the fault condition in accordance with identifying the fault condition” are recited at a high level of generality. These elements amount to receiving or transmitting data using generic computers and are well-understood, routine, conventional activity (MPEP 2106.05(d), subsection II).
Regarding claim(s) 2-6, 8, 10-13, 15, 17-19, 21, the additional elements are not sufficient to amount to significantly more than the judicial exception because they simply apply the exception using a generic computer.
Therefore, claim(s) 1-6, 8-13, 15-19, 21 recite an abstract idea without significantly more, and are not patent eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-6, 9-13, 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thornley et al. (US 20190278651 A1).
Thornley discloses:
2. (New) An apparatus, comprising:
a memory system (information handling system; fig 1: 141) comprising one or more memory arrays (115; 180); and
control circuitry coupled with the memory system and configured to cause the apparatus to:
receive, from a host system, a command to perform an operation on the one or more memory arrays (115; 180) of the memory system; (par 9: The SBIOS executing on the host processing device may be configured to respond to the SMI by entering system management mode (SMM), and may also be configured to save the current context of the host processing device (e.g. CPU context information such as copies of last CPU registers) at the time of system hang failure into SMM “save state” region of system management RAM (SMRAM))
identify, by the memory system, a fault condition of the memory system associated with performing the operation in response to receiving the command; (par 9: Examples of context information that may be so extracted from the SMM “save state” region and saved as fault information to NVM include, but is not limited to, information regarding location in processing device code where system hang is occurring such as failing assembly instruction pointer, CPU registers, stack frame, etc; par 9: be configured to save the current context of the host processing device)
transmit, from the memory system to the host system, a message that indicates the fault condition in accordance with identifying the fault condition. (par 9: The SBIOS executing on the host processing device may be configured to respond to the SMI by entering system management mode (SMM), and may also be configured to save the current context of the host processing device (e.g. CPU context information such as copies of last CPU registers) at the time of system hang failure into SMM “save state” region of system management RAM (SMRAM), and then to extract at least a portion of this host processing device context information from SMRAM and save it as fault information into NVM such as NVRAM.) [examiner’s note: transmitting context information from 115/180 to 107, it must go through host 105 according to fig 1.]
3. (New) The apparatus of claim 2, wherein the control circuitry is further configured to cause the apparatus to: generate the message that indicates the fault condition in accordance with identifying the fault condition. (par 9: The SBIOS executing on the host processing device may be configured to respond to the SMI by entering system management mode (SMM), and may also be configured to save the current context of the host processing device (e.g. CPU context information such as copies of last CPU registers) at the time of system hang failure into SMM “save state” region of system management RAM (SMRAM), and then to extract at least a portion of this host processing device context information from SMRAM and save it as fault information into NVM such as NVRAM.) [examiner’s note: having context information in 115/180, then transmitting context information from 115/180 to 107 via 105.]
4. (New) The apparatus of claim 2, wherein the control circuitry is further configured to cause the apparatus to: generate a code associated with the fault condition that signals that the fault condition occurred in accordance with identifying the fault condition. (par 9: SMI; SMM; context information that may be so extracted from the SMM “save state” region and saved as fault information to NVM include, but is not limited to, information regarding location in processing device code where system hang is occurring such as failing assembly instruction pointer, CPU registers, stack frame, etc)
5. (New) The apparatus of claim 2, wherein the control circuitry is further configured to cause the apparatus to: identify information associated with the fault condition in accordance with identifying the fault condition. [examiner’s note: SMI event requires setting of a global bit and an individual control bit on registers.]
6. (New) The apparatus of claim 5, wherein the information associated with the fault condition comprises a time at which the fault condition occurred (par 8: watchdog timer event; par 9: to save the current context of the host processing device (e.g. CPU context information such as copies of last CPU registers) at the time of system hang failure into SMM “save state” region of system management RAM (SMRAM), and then to extract at least a portion of this host processing device context information from SMRAM and save it as fault information into NVM such as NVRAM), a duration of the fault condition, a temperature of the apparatus, or a combination thereof.
Claim(s) 9-13 is/are rejected as being the medium implemented by the apparatus of claim(s) 2-6, and is/are rejected on the same grounds.
Claim(s) 16-19 is/are rejected as being the method implemented by the apparatus of claim(s) 2-5, and is/are rejected on the same grounds.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8, 14-15, 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thornley et al. (US 20190278651 A1) in view of SIMIONESCU et al. (US 20200387449 A1).
7. (New) The apparatus of claim 2, wherein the control circuitry is further configured to cause the apparatus to:
However, Thornley does not explicitly disclose, while SIMIONESCU teaches:
deallocate buffer resources associated with data received from the host system. (fig 8: 822; par 111)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine identifying an error of Thornley with error detection of SIMIONESCU. One of ordinary skill in the art would have been motivated to do so in order to return an indication of the result. (SIMIONESCU: par 112)
Modified Thornley discloses:
8. (New) The apparatus of claim 7, wherein the control circuitry is further configured to cause the apparatus to:
However, Thornley does not explicitly disclose, while SIMIONESCU teaches:
receive a notification in response to deallocating the buffer resources associated with the data received from the host system. (fig 8: 822-> 824)
Claim(s) 14-15 is/are rejected as being the medium implemented by the apparatus of claim(s) 7-8, and is/are rejected on the same grounds.
Claim(s) 20-21 is/are rejected as being the method implemented by the apparatus of claim(s) 7-8, and is/are rejected on the same grounds.
Response to Remarks
Applicant's Remarks have been fully considered but they are not persuasive.
Regarding the rejections under 101, the Remarks state, “the Specification explains that where a fault condition is not communicated to the host system,… because "the host system may be unresponsive or unaware of the status (e.g., state) of the memory system, which may allow the memory system to continue performing operations after the fault condition occurs." Id.1 [0011]… These features place both the identification of the fault condition and the reporting of the fault condition at the memory system, and tie the transmission of the message to the identification of the fault condition, such that the host system is informed of the fault condition rather than detecting an unresponsive memory system after expiration of a time-out period.” However, the examiner respectfully disagrees. Claims 2, 9, 16 do not teach the improvements described in the Remarks. Claim 2 recites, “receive, from a host system, a command to perform an operation on the one or more memory arrays of the memory system.” However, the operation is not clear. The host could, for example, give a command to reset or clear memory arrays for critical error detection. Then, the improvement “that the host system is informed of the fault condition rather than detecting an unresponsive memory system after expiration of a time-out period” does not exist.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHERINE LIN whose telephone number is (571)431-0706. The examiner can normally be reached Monday-Friday; 8 a.m. - 5 p.m. EST.
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/KATHERINE LIN/Primary Examiner, Art Unit 2113
