DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12095495. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claims in the pending Application are transparently found in US 12095495 with obvious wording variations. See the table below for comparison:
Pending Application 18/814266
US 12095495
1. A phased array system, comprising: receive circuitry comprising a low noise amplifier; phase shift circuitry configured to shift a phase of a signal received at the low noise amplifier, the phase shift circuitry comprising a switching network, the switching network comprising a first switch and a first shunt switch configured to couple a processor to a first end of an inductor of the low noise amplifier, and a second switch and a second shunt switch configured to couple the processor to a second end of the inductor of the low noise amplifier.
2. The phased array system of claim 1, wherein coupling the processor to the first end of the inductor of the low noise amplifier applies a 180-degree phase shift to a signal received at the receive circuitry.
3. The phased array system of claim 1, wherein coupling the processor to the second end of the inductor of the low noise amplifier applies a 0-degree phase shift to a signal received at the receive circuitry.
4. The phased array system of claim 1, comprising a differential transmission line configured to couple the switching network to a port of the low noise amplifier.
8. The phased array system of claim 1, comprising a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch.
9. The phased array system of claim 8, wherein the first shunt switch and the second shunt switch are coupled to a port of the low noise amplifier.
15. A receiver, comprising: a transformer electrically coupled to an amplifier; and a switching network electrically coupled to the transformer, the switching network configured to activate a first switch to apply a first phase shift to a first signal input to the amplifier, and activate a second switch to apply a second phase shift to a second signal input to the amplifier.
1. A transceiver, comprising: a transmitter comprising a first transformer; a receiver comprising a second transformer; and isolation and phase-shifting circuitry comprising: a first switch configured to enable a first phase shift by coupling processing circuitry to a first end of the first transformer of the transmitter, a second switch configured to enable a second phase shift by coupling the processing circuitry to a second end of the first transformer of the transmitter, a third switch configured to enable a third phase shift by coupling the processing circuitry to a first end of the second transformer of the receiver, and a fourth switch configured to enable a fourth phase shift by coupling the processing circuitry to a second end of the second transformer of the receiver.
2. The transceiver of claim 1, wherein the first phase shift comprises 0 degrees.
3. The transceiver of claim 1, wherein the second phase shift comprises 180 degrees.
5. The phased array system of claim 1, wherein the switching network is coupled to another inductor.
6. The transceiver of claim 1, comprising an inductor coupling the isolation and phase-shifting circuitry to the processing circuitry, the inductor configured to absorb excess reactive power of the first switch and the second switch, the third switch and the fourth switch, or both.
6. The phased array system of claim 5, wherein the other inductor comprises an inductance of 50 picohenries to 100 picohenries.
7. The phased array system of claim 1, wherein the first shunt switch and the second shunt switch are disposed 100 micrometers to 250 micrometers from a port of the low noise amplifier.
7. The transceiver of claim 6, wherein the inductor has an inductance of 100 picohenries to 150 picohenries.
10. A method, comprising: activating a first switch to couple processing circuitry to a first end of an inductor of a receiver and deactivating a second switch to decouple the processing circuitry from a second end of the inductor to apply a first phase shift to a signal; activating the second switch to couple the processing circuitry to the second end of the inductor and deactivating the first switch to decouple the processing circuitry from the first end of the inductor to apply a second phase shift to the signal; and receiving the signal from the receiver based on the first switch and the second switch being activated.
13. The method of claim 10, wherein activating the first switch applies a phase shift of 180-degrees to the signal.
14. The method of claim 10, wherein activating the second switch applies a phase shift of 0-degrees to the signal.
11. A method of performing isolation and phase-shifting, comprising: activating a first switch to cause a first phase shift by coupling processing circuitry to a first end of a first transformer of a transmitter; deactivating a second switch to decouple the processing circuitry from a second end of the first transformer of the transmitter; deactivating a third switch to decouple the processing circuitry from a first end of a second transformer of a receiver; and deactivating a fourth switch to decouple the processing circuitry from a second end of the second transformer of the receiver.
2. The transceiver of claim 1, wherein the first phase shift comprises 0 degrees.
3. The transceiver of claim 1, wherein the second phase shift comprises 180 degrees.
11. The method of claim 10, comprising activating a first shunt switch configured to create a short circuit at the second end of the inductor based on activating the first switch.
12. The method of claim 10, comprising activating a second shunt switch configured to create a short circuit at the first end of the inductor based on activating the second switch.
12. The method of performing isolation and phase-shifting of claim 11, comprising: deactivating the first switch to decouple the processing circuitry from the first end of the first transformer of the transmitter; activating the second switch to cause a second phase shift by coupling the processing circuitry to a second end of the first transformer of the transmitter; deactivating the third switch to decouple the processing circuitry from the first end of the second transformer of the receiver; and deactivating the fourth switch to decouple the processing circuitry from the second end of the second transformer of the receiver.
16. The receiver of claim 15, wherein the switching network is coupled between the transformer and single-ended transmission lines.
9. The transceiver of claim 8, comprising one or more single-ended transmission lines coupling the first switch to the one or more phase shifters, the second switch to the one or more phase shifters, or both.
17. The receiver of claim 15, comprising an inductor coupled to the switching network to processing circuitry.
6. The transceiver of claim 1, comprising an inductor coupling the isolation and phase-shifting circuitry to the processing circuitry, the inductor configured to absorb excess reactive power of the first switch and the second switch, the third switch and the fourth switch, or both.
18. The receiver of claim 17, wherein the inductor comprises an inductance of between 100 picohenries and 150 picohenries.
7. The transceiver of claim 6, wherein the inductor has an inductance of 100 picohenries to 150 picohenries.
19. The receiver of claim 17, wherein the inductor is configured to absorb excess reactive power associated with the first switch and the second switch.
8. The transceiver of claim 1, comprising one or more phase shifters coupling the isolation and phase-shifting circuitry to the processing circuitry, the one or more phase shifters configured to shift a phase of a signal sent from the processing circuitry, a signal sent from the receiver, or both.
20. The receiver of claim 15, comprising phase shifting circuitry coupled between the switching network and a processor, the phase shifting circuitry configured to apply a 45-degree phase shift, a 90-degree phase shift, or a 135-degree phase shift to the first signal or the second signal.
16. The phased array system of claim 15, wherein the first phase shift comprises a 0-degree phase shift.
17. The phased array system of claim 15, wherein the second phase shift comprises a 180-degree phase shift.
18. The phased array system of claim 15, wherein the third phase shift comprises a 0-degree phase shift.
19. The phased array system of claim 15, wherein the fourth phase shift comprises a 180-degree phase shift.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12250019. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claims in the pending Application are transparently found in US 12250019 with obvious wording variations. See the table below for comparison:
Pending Application 18/814266
US 12250019
1. A phased array system, comprising: receive circuitry comprising a low noise amplifier; phase shift circuitry configured to shift a phase of a signal received at the low noise amplifier, the phase shift circuitry comprising a switching network, the switching network comprising a first switch and a first shunt switch configured to couple a processor to a first end of an inductor of the low noise amplifier, and a second switch and a second shunt switch configured to couple the processor to a second end of the inductor of the low noise amplifier.
5. The phased array system of claim 1, wherein the switching network is coupled to another inductor.
6. The phased array system of claim 5, wherein the other inductor comprises an inductance of 50 picohenries to 100 picohenries.
7. The phased array system of claim 1, wherein the first shunt switch and the second shunt switch are disposed 100 micrometers to 250 micrometers from a port of the low noise amplifier.
11. A phased array system comprising: a transceiver comprising a transformer electrically coupled to an amplifier, the transformer comprising a first winding and a second winding; and phase shift circuitry comprising a switching network electrically coupled to the transformer, the switching network configured to activate a first switch and deactivate a second switch to couple processing circuitry to a first end of the first winding of the transformer to apply a first phase shift to a signal input to the amplifier, and activate the second switch and deactivate the first switch to couple the processing circuitry to a second end of the first winding of the transformer to apply a second phase shift to the signal input to the amplifier.
2. The phased array system of claim 1, wherein coupling the processor to the first end of the inductor of the low noise amplifier applies a 180-degree phase shift to a signal received at the receive circuitry.
14. The phased array system of claim 11, wherein the first switch is configured to apply a 180 degree phase shift to the signal input to the amplifier.
3. The phased array system of claim 1, wherein coupling the processor to the second end of the inductor of the low noise amplifier applies a 0-degree phase shift to a signal received at the receive circuitry.
15. The phased array system of claim 11, wherein the second switch is configured to apply a 0 degree phase shift to the signal input to the amplifier.
4. The phased array system of claim 1, comprising a differential transmission line configured to couple the switching network to a port of the low noise amplifier.
13. The phased array system of claim 11, wherein the amplifier comprises a low noise amplifier.
8. The phased array system of claim 1, comprising a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch.
9. The phased array system of claim 8, wherein the first shunt switch and the second shunt switch are coupled to a port of the low noise amplifier.
8. The transceiver of claim 1, comprising: a first transmission line coupled between the first transformer and the first switching network; and a second transmission line coupled between the second transformer and the second switching network.
9. The transceiver of claim 8, wherein the first transmission line, the second transmission line, or both comprise a differential transmission line.
10. A method, comprising: activating a first switch to couple processing circuitry to a first end of an inductor of a receiver and deactivating a second switch to decouple the processing circuitry from a second end of the inductor to apply a first phase shift to a signal; activating the second switch to couple the processing circuitry to the second end of the inductor and deactivating the first switch to decouple the processing circuitry from the first end of the inductor to apply a second phase shift to the signal; and receiving the signal from the receiver based on the first switch and the second switch being activated.
11. The method of claim 10, comprising activating a first shunt switch configured to create a short circuit at the second end of the inductor based on activating the first switch.
17. A method comprising: receiving a first indication to send a signal via a transmitter comprising a transformer, the transformer comprising a first winding and a second winding; receiving a second indication to apply phase shift to the signal; activating a first set of switches and deactivating a second set of switches of a switching network to couple processing circuitry to a first end of the first winding of the transformer to apply a first phase shift to the signal if the phase shift is greater than a predetermined phase angle; and activating the second set of switches and deactivating the first set of switches of the switching network to couple the processing circuitry to a second end of the first winding of the transformer to apply a second phase shift to the signal if the phase shift is not greater than the predetermined phase angle.
13. The method of claim 10, wherein activating the first switch applies a phase shift of 180-degrees to the signal.
19. The method of claim 17, wherein the first phase shift comprises a 180 degree phase shift.
14. The method of claim 10, wherein activating the second switch applies a phase shift of 0-degrees to the signal.
20. The method of claim 17, wherein the second phase shift comprises a 0 degree phase shift.
15. A receiver, comprising: a transformer electrically coupled to an amplifier; and a switching network electrically coupled to the transformer, the switching network configured to activate a first switch to apply a first phase shift to a first signal input to the amplifier, and activate a second switch to apply a second phase shift to a second signal input to the amplifier.
16. The receiver of claim 15, wherein the switching network is coupled between the transformer and single-ended transmission lines.
17. The receiver of claim 15, comprising an inductor coupled to the switching network to processing circuitry.
18. The receiver of claim 17, wherein the inductor comprises an inductance of between 100 picohenries and 150 picohenries.
19. The receiver of claim 17, wherein the inductor is configured to absorb excess reactive power associated with the first switch and the second switch.
20. The receiver of claim 15, comprising phase shifting circuitry coupled between the switching network and a processor, the phase shifting circuitry configured to apply a 45-degree phase shift, a 90-degree phase shift, or a 135-degree phase shift to the first signal or the second signal.
1. A transceiver comprising: a first amplifier having a first signal input; a second amplifier having a second signal input; a first transformer electrically coupled to the first amplifier; a second transformer electrically coupled to the second amplifier; a first switching network having a first switch and a second switch, and being electrically coupled to the first transformer, the first switching network configured to activate the first switch to apply a first phase shift to the first signal input of the first amplifier, and activate the second switch to apply a second phase shift to the first signal input of the first amplifier; and a second switching network having a third switch and a fourth switch, and being electrically coupled to the second transformer, the second switching network configured to activate the third switch to apply the first phase shift to the second signal input of the second amplifier, and activate the fourth switch to apply the second phase shift to the second signal input of the second amplifier.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 10-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220231391, hereinafter “Wang”) and further in view of Varonen et al. (US 20200403584, hereinafter “Varonen”).
Regarding claim 1, Wang discloses,
A phased array system (FIG. 10 is a block diagram illustrating an exemplary phased array system 1000), comprising:
receive circuitry comprising a low noise amplifier (the system 1000 may include a receiver 1050 and a plurality of low-noise amplifiers (LNAs) 1020, [0074]);
phase shift circuitry configured to shift a phase of a signal received at the low noise amplifier (The phase shifters 1016b may be substantially similar to the phase shifters 1016a and may apply various phase shifts (e.g., 45°, 90°, 180°, etc.) to the received signals [0076]), the phase shift circuitry comprising a switching network (The phase shifter circuitry 200 may utilize a switched transformer topology to provide two output phase states with a phase difference of about 180 degrees [0036]), the switching network comprising
a first switch (Fig. 3A; 214a) and a first shunt switch (shunt FETs 314a; Fig. 3A) and a second switch (Fig. 3A; 224a) and a second shunt switch (shunt FETs 324a; Fig. 3A).
However, Wang does not explicitly disclose, the switching network is connected to the first and second end of the inductor of the low noise amplifier.
In the same field of endeavor, Varonen discloses, the switching network is connected to the first and second end of the inductor (The secondary windings 514, 519 are connected at one end to a first output port 533, 537 and at the other to a second output port 535, 539. Connected to each end of the secondary winding 514, 519 is a switch 520, 521, 524, 525 connected at one end to the secondary winding, Fig. 5 and Fig. 6 and Para. [0048]-[0052]) of the low noise amplifier (The transformer based switch of FIG. 5 and Fig. 6 would find use across a variety of PALNA applications).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Wang by specifically providing the switching network is connected to the first and second end of the inductor of the low noise amplifier, as taught by Varonen for the purpose of providing a technique for improved linearity in a compact switch while also providing low-insertion loss, especially useful for PALNA systems [0002].
Regarding claim 2, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), further Wang discloses,
wherein coupling the processor to the first end of the inductor of the low noise amplifier applies a 180-degree phase shift (The present disclosure describes mechanisms for providing a 180 degree phase shifter in a manner that can address the insertion loss, phase flatness [0024]; the phase shifter circuitry 200 may provide two output phase states (a first output phase state from the first signal path 201 and a second output phase state from the second signal path 203) with a relative phase difference of about 180 degrees [0039]) to a signal received at the receive circuitry (The switches 1022 may be selected to couple various antenna elements 1025 to the LNAs 1020. The LNAs 1020 may amplify the received signals. The phase shifters 1016b may be substantially similar to the phase shifters 1016a and may apply various phase shifts (e.g., 45°, 90°, 180°, etc.) to the received signals [0076]).
Regarding claim 3, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), further Wang discloses,
wherein coupling the processor to the second end of the inductor of the low noise amplifier applies a 0-degree phase shift (For the positively coupled transformer, the voltage across the primary coil and the voltage across the secondary coil are in-phase (providing a 0 degree phase-shift) [0024]) to a signal received at the receive circuitry (The switches 1022 may be selected to couple various antenna elements 1025 to the LNAs 1020. The LNAs 1020 may amplify the received signals. The phase shifters 1016b may be substantially similar to the phase shifters 1016a and may apply various phase shifts (e.g., 45°, 90°, 180°, etc.) to the received signals [0076]).
Regarding claim 10, Wang discloses,
A method (FIG. 11 is a flow diagram illustrating an exemplary method 1100 for performing phase-shifting [0080]), comprising:
activating a first switch to couple processing circuitry and deactivating a second switch to decouple the processing circuitry apply a first phase shift to a signal (the method 1100 may further include closing a first switch coupled between the first node and the positively coupled transformer and opening a second switch coupled between the first node and the negatively coupled transformer to select, in response to the first control signal, the first signal path for transmitting the first signal at 1104. In some aspects, the first switch may correspond to the switch 214a or the switch 214b, and the second switch may correspond to the switch 224a or the switch 224b, [0085]-[0086]);
activating the second switch to couple the processing circuitry and deactivating the first switch to decouple the processing circuitry to apply a second phase shift to the signal (the method 1100 may further include opening a first switch coupled between the first node and the positively coupled transformer and closing a second switch coupled between the first node and the negatively coupled transformer to select the second signal path for transmitting the second signal in response to the second control signal at 1108. In some aspects, the first switch may correspond to the switch 214a or the switch 214b, and the second switch may correspond to the switch 224a or the switch 224b, [0085]-[0086]); and
receiving the signal from the receiver (a signal may be received by the antenna array 1024 via the antenna elements 1025. The switches 1022 may be selected to couple various antenna elements 1025 to the LNAs 1020 [0076]) based on the first switch and the second switch being activated (a single one of the first signal path 201 or the second signal path 203 may be selected at any given time. In other words, the phase shifter circuitry 200 may be configured to conduct an input signal via the first signal path 201 to provide a first output signal at the output node 204, or alternatively, via the second signal path 203 to provide a second output signal at the output node 204 [0040]).
However, Wang does not explicitly disclose, the switching network is connected to the first and second end of the inductor of the low noise amplifier.
In the same field of endeavor, Varonen discloses, the switching network is connected to the first and second end of the inductor (The secondary windings 514, 519 are connected at one end to a first output port 533, 537 and at the other to a second output port 535, 539. Connected to each end of the secondary winding 514, 519 is a switch 520, 521, 524, 525 connected at one end to the secondary winding, Fig. 5 and Fig. 6 and Para. [0048]-[0052]) of the low noise amplifier (The transformer based switch of FIG. 5 and Fig. 6 would find use across a variety of PALNA applications).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Wang by specifically providing the switching network is connected to the first and second end of the inductor of the low noise amplifier, as taught by Varonen for the purpose of providing a technique for improved linearity in a compact switch while also providing low-insertion loss, especially useful for PALNA systems [0002].
Regarding claim 11, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 10), further Wang discloses,
activating a first shunt switch configured to create a short circuit at the second end of the inductor based on activating the first switch (As shown in FIG. 3A, the phase shifter circuitry 300 may further include shunt FETs 314a, 314b, 324a, and 324b shown as N5, N6, N7, and N8, respectively. The shunt FET 314a is arranged on a shunt path coupled to the first signal path 201, for example, at a node between the FET 214a and the positively coupled transformer 212. The shunt FET 314b is arranged on a shunt path coupled to the first signal path 201, for example, at a node between the positively coupled transformer 212 and the FET 214b [0047]-[0048]).
Regarding claim 12, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 10), further Wang discloses,
activating a second shunt switch configured to create a short circuit at the first end of the inductor based on activating the second switch (As shown in FIG. 3A, the phase shifter circuitry 300 may further include shunt FETs 314a, 314b, 324a, and 324b shown as N5, N6, N7, and N8, respectively. The shunt FET 314a is arranged on a shunt path coupled to the first signal path 201, for example, at a node between the FET 214a and the positively coupled transformer 212. The shunt FET 314b is arranged on a shunt path coupled to the first signal path 201, for example, at a node between the positively coupled transformer 212 and the FET 214b [0047]-[0048]).
Regarding claim 13, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 10), further Wang discloses,
wherein activating the first switch applies a phase shift of 180-degrees to the signal (The present disclosure describes mechanisms for providing a 180 degree phase shifter in a manner that can address the insertion loss, phase flatness [0024]; the phase shifter circuitry 200 may provide two output phase states (a first output phase state from the first signal path 201 and a second output phase state from the second signal path 203) with a relative phase difference of about 180 degrees [0039]; The switches 1022 may be selected to couple various antenna elements 1025 to the LNAs 1020. The LNAs 1020 may amplify the received signals. The phase shifters 1016b may be substantially similar to the phase shifters 1016a and may apply various phase shifts (e.g., 45°, 90°, 180°, etc.) to the received signals [0076]).
Regarding claim 14, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 10), further Wang discloses,
wherein activating the second switch applies a phase shift of 0-degrees to the signal (For the positively coupled transformer, the voltage across the primary coil and the voltage across the secondary coil are in-phase (providing a 0 degree phase-shift) [0024]; The switches 1022 may be selected to couple various antenna elements 1025 to the LNAs 1020. The LNAs 1020 may amplify the received signals. The phase shifters 1016b may be substantially similar to the phase shifters 1016a and may apply various phase shifts (e.g., 45°, 90°, 180°, etc.) to the received signals [0076]).
Regarding claim 15, Wang discloses,
A receiver (the system 1000 may include a receiver 1050 and a plurality of low-noise amplifiers (LNAs) 1020, [0074]), comprising:
a transformer electrically coupled to an amplifier (four receive paths (e.g., each including a DSA 1014b, a phase shifter 1016b, and an LNA 1020) in the system 1000, a phased array system can include any suitable number of paths.. each receive path may include a phase shifter, the switched transformer-based phase shifter circuitries disclosed herein can advantageously reduce the size of a phased array system or a beamforming integrated device [0078]); and
a switching network electrically coupled to the transformer (The phase shifter circuitry 200 may utilize a switched transformer topology to provide two output phase states with a phase difference of about 180 degrees [0036]),
the switching network configured to activate a first switch to apply a first phase shift (the method 1100 may further include closing a first switch coupled between the first node and the positively coupled transformer and opening a second switch coupled between the first node and the negatively coupled transformer to select, in response to the first control signal, the first signal path for transmitting the first signal at 1104. In some aspects, the first switch may correspond to the switch 214a or the switch 214b, and the second switch may correspond to the switch 224a or the switch 224b, [0085]-[0086]), and activate a second switch to apply a second phase shift (the method 1100 may further include opening a first switch coupled between the first node and the positively coupled transformer and closing a second switch coupled between the first node and the negatively coupled transformer to select the second signal path for transmitting the second signal in response to the second control signal at 1108. In some aspects, the first switch may correspond to the switch 214a or the switch 214b, and the second switch may correspond to the switch 224a or the switch 224b, [0085]-[0086]).
However, Wang does not explicitly disclose, the switching network is connected to the first and second input of the low noise amplifier.
In the same field of endeavor, Varonen discloses, the switching network is connected to the first and second input (The secondary windings 514, 519 are connected at one end to a first output port 533, 537 and at the other to a second output port 535, 539. Connected to each end of the secondary winding 514, 519 is a switch 520, 521, 524, 525 connected at one end to the secondary winding, Fig. 5 and Fig. 6 and Para. [0048]-[0052]) of the low noise amplifier (The transformer based switch of FIG. 5 and Fig. 6 would find use across a variety of PALNA applications).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Wang by specifically providing the switching network is connected to the first and second input of the low noise amplifier, as taught by Varonen for the purpose of providing a technique for improved linearity in a compact switch while also providing low-insertion loss, especially useful for PALNA systems [0002].
Regarding claim 20, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 15), further Wang discloses,
phase shifting circuitry coupled between the switching network and a processor, the phase shifting circuitry configured to apply a 45-degree phase shift, a 90-degree phase shift, or a 135-degree phase shift to the first signal or the second signal (the phase shifter circuitry 910 may be configured to provide a phase-shift of 0° or 90° based on a control signal 915 (shown as Vctrl5) being a logic high or a logic low, respectively, or vice versa. The phase shifter circuitry 920 may be configured to provide a phase-shift of 0° or 5.6° based on a control signal 911 (shown as Vctrl1) being a logic high or a logic low, respectively, or vice versa. The phase shifter circuitry 930 may be configured to provide a phase-shift of 0° or 180° based on a control signal 916 (shown as Vctrl6) being a logic high or a logic low, respectively, or vice versa. The phase shifter circuitry 940 may be configured to provide a phase-shift of 0° or 22° based on a control signal 913 (shown as Vctrl3) being a logic high or a logic low, respectively, or vice versa. The phase shifter circuitry 950 may be configured to provide a phase-shift of 0° or 11° based on a control signal 912 (shown as Vctrl2) being a logic high or a logic low, respectively, or vice versa. The phase shifter circuitry 960 may be configured to provide a phase-shift of 0° or 45° based on a control signal 914 [0068]).
Claims 4, 8, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Varonen, and further in view of WO 2020035634 (hereinafter “Varonen2).
Regarding claim 4, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), however the combination Wang and Varonen does not disclose, a differential transmission line configured to couple the switching network to a port of the low noise amplifier.
In the same field of endeavor, Varonen2 discloses, a differential transmission line configured to couple the switching network to a port of the low noise amplifier (there is provided a differential transmission line based switch configured to be connected to a power amplifier (PA) and/or Low Noise Amplifier (LNA), said transmission line [0004]; FIGURE 2 shows a differential transmission lined based switch 200 according to certain embodiments of the present invention. In contrast to the embodiment of figure 1, the first 201 and second 202 circuits of the switch 200 of figure 2 each contain two transmission lines [0015]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Wang and Varonen a differential transmission line configured to couple the switching network to a port of the low noise amplifier, as taught by Varonen2 for the purpose of providing a transmission line based switch having a much greater linearity than traditional transistor based switches especially in the case of PALNA applications [0011].
Regarding claim 8, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), however the combination Wang and Varonen does not disclose, a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch.
In the same field of endeavor, Varonen2 discloses, a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch (the differential transmission line based switch 100 comprises a first input port 131 conductively connected to: an input of a first transmission line 111 of a first circuit 101 and an input of a first transmission line 112 of a second circuit 102….. he first switch 122 of the second circuit 102 is conductively connected at one end to an output of the first transmission line 112 of the second circuit 102, the other end of the first switch 122 of the second circuit 102 being configured to be connected to a ground potential, Fig. 1 and [0012]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Wang and Varonen a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch, as taught by Varonen2 for the purpose of providing a transmission line based switch having a much greater linearity than traditional transistor based switches especially in the case of PALNA applications [0011].
Regarding claim 9, the combination of Wang, Varonen and Varonen2 discloses everything claimed as applied above (see claim 8), in addition Varonen discloses,
wherein the first shunt switch and the second shunt switch are coupled to a port of the low noise amplifier (an LNA output port 235 connected to the other end of the quarter wavelength impedance 240, and at least one LNA circuit switch 220 connected at one end to the LNA output port 235, the other end being configured to be connected to a ground potential, Fig. 2 and [0029]).
Regarding claim 16, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 15), however the combination Wang and Varonen does not disclose, wherein the switching network is coupled between the transformer and single-ended transmission lines.
In the same field of endeavor, Varonen2 discloses, wherein the switching network is coupled between the transformer and single-ended transmission lines (the differential transmission line based switch 100 comprises a first input port 131 conductively connected to: an input of a first transmission line 111 of a first circuit 101 and an input of a first transmission line 112 of a second circuit 102….. he first switch 122 of the second circuit 102 is conductively connected at one end to an output of the first transmission line 112 of the second circuit 102, the other end of the first switch 122 of the second circuit 102 being configured to be connected to a ground potential, Fig. 1 and [0012]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Wang and Varonen wherein the switching network is coupled between the transformer and single-ended transmission lines, as taught by Varonen2 for the purpose of providing a transmission line based switch having a much greater linearity than traditional transistor based switches especially in the case of PALNA applications [0011].
Claims 5, 6, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Varonen, and further in view of Yehezkely et al. (US 20150207536, hereinafter “Yehez”).
Regarding claim 5, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), however the combination Wang and Varonen does not disclose, wherein the switching network is coupled to another inductor.
In the same field of endeavor, Yehezkely discloses, wherein the switching network is coupled to another inductor (FIG. 4 includes an input 402, an impedance circuit 404, a common node 406, a plurality of switches 408 (e.g., 4 switches 410-416) and a plurality of outputs 418 (e.g. 4 outputs 420-426), [0027]-[0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of Wang and Varonen by specifically providing wherein the switching network is coupled to another inductor, as taught by Yehez for the purpose of improving a signal-to-noise ratio of RF signals by reducing signal loss as compared to a static summing/distribution network that has "open" paths that introduce signal loss [0026].
Regarding claim 6, the combination of Wang, Veronen and Yehezkely discloses everything claimed as applied above (See claim 5), further Yehez discloses, wherein the other inductor comprises an inductance of 50 picohenries to 100 picohenries (the inductors 430-436 may be selected based on the switch capacitance and to match (or substantially match) the input impedance (e.g., of the impedance circuit 404, which includes the 100 picohenry (pH) inductor [0031]).
Regarding claim 17, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 15), however the combination Wang and Varonen does not disclose, w an inductor coupled to the switching network to processing circuitry.
In the same field of endeavor, Yehezkely discloses, an inductor coupled to the switching network to processing circuitry. (FIG. 4 includes an input 402, an impedance circuit 404, a common node 406, a plurality of switches 408 (e.g., 4 switches 410-416) and a plurality of outputs 418 (e.g. 4 outputs 420-426), [0027]-[0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of Wang and Varonen by specifically providing an inductor coupled to the switching network to processing circuitry, as taught by Yehez for the purpose of improving a signal-to-noise ratio of RF signals by reducing signal loss as compared to a static summing/distribution network that has "open" paths that introduce signal loss [0026].
Regarding claim 18, the combination of Wang, Veronen and Yehezkely discloses everything claimed as applied above (See claim 17), further Yehez discloses, wherein the other inductor comprises an inductance of 50 picohenries to 100 picohenries (the inductors 430-436 may be selected based on the switch capacitance and to match (or substantially match) the input impedance (e.g., of the impedance circuit 404, which includes the 100 picohenry (pH) inductor [0031]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Varonen, and further in view of Feng et al. (US 20030090350, hereinafter “Feng”).
Regarding claim 7, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 1), however the combination Wang and Varonen does not disclose, wherein the first shunt switch and the second shunt switch are disposed 100 micrometers to 250 micrometers from a port of the low noise amplifier.
In the same field of endeavor, Feng discloses, wherein the first shunt switch and the second shunt switch (A non-zero dielectric thickness corresponds to a capacitively coupled shunt switch, i.e., effectively a low-pass filter or an RF short [0027]) are disposed 100 micrometers to 250 micrometers from a port of the low noise amplifier (A width of the top electrodes 30 was chosen at 100 .mu.M and 150 .mu.m. Combined with the different coplanar waveguide structures, six different impedance sets are available [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of Wang and Varonen by specifically providing wherein the first shunt switch and the second shunt switch are disposed 100 micrometers to 250 micrometers from a port of the low noise amplifier, as taught by Feng for the purpose providing an improved microelectromechanical switch for RF communication device [0040].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Varonen, and further in view of Srihari et al. (US 20160182037, hereinafter “Srihari”).
Regarding claim 19, the combination of Wang and Varonen discloses everything claimed as applied above (see claim 17), however the combination Wang and Varonen does not disclose, wherein the inductor is configured to absorb excess reactive power associated with the first switch and the second switch.
In the same field of endeavor, Srihari discloses, wherein the inductor is configured to absorb excess reactive power associated with the first switch and the second switch (the present invention circumvent the problem of leakage of the SPDT switch described above, thereby improving the isolation and reducing the insertion loss, when compared to the conventional SPDT switch. The resonant circuit in parallel to the FET resonates out the capacitance of the FET, resulting in higher isolation. Said differently, the capacitance of the FET is essentially cancelled out due to the configuration of the circuit [0016]-[0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of Wang and Varonen by specifically providing wherein the inductor is configured to absorb excess reactive power associated with the first switch and the second switch, as taught by Srihari for the purpose of providing a parallel resonant LC network across each of the series-shunt branch FETs in an RF circuit is provided for improved insertion loss, switch isolation, and out of band harmonics [0014].
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 12009564: A phased array element includes a transmit portion having a plurality of amplifier paths, each amplifier path having a driver amplifier and a power amplifier, a first transformer coupled to the power amplifier of a first amplifier path of the plurality of amplifier paths and a second transformer coupled to the power amplifier of a second amplifier path of the plurality of amplifier paths, a secondary winding of each of the first transformer and the second transformer coupled together by a common transformer segment.
US 11546010: One example includes a switch system. The system includes a first signal port and a second signal port. The system also includes a first switching path arranged between the first and second signal ports. The first switching path includes at least one first switch and at least one of the at least one first switch being configured as a high-speed switching device. The system further includes a second switching path arranged between the first and second signal ports in parallel with the first switching path.
US 11349503: An apparatus is disclosed for phase-shifting signals with a compensation circuit. In example implementations, an apparatus for phase-shifting signals includes a phase shifter having a first port and a second port. The phase shifter also includes a signal phase generator, a compensation circuit, and a vector modulator. The compensation circuit includes a first capacitor with a first capacitance and a second capacitor with a second capacitance. The first capacitance is different from the second capacitance.
Conclusion
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/GOLAM SOROWAR/ Primary Examiner, Art Unit 2641
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