Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 5, 7-12, 14-17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20220321066 A1, cited by the applicant) in view of Lee (US 11652453 B2), hereafter referred to as “Hu” and “Lee”, respectively.
Regarding claims 1, 2, 3, 5, 7-12, 14-17, 19, and 20 in the embodiment of Figs. 1 and 2, Hu discloses:
An apparatus (Figs. 1 and 2), comprising:
a load inductor (the main coil of load balun 20 (i.e. left of 20)) having a first inductor node at a first end(first balun input 21), a second inductor node at a second end (second balun input 22), and a center inductor node (connection to power supply terminal 23) between the first end and the second end;
a first switch (DC blocking circuit 30, includes adjustable capacitive network per paragraph [0056], which may consist of switches in series, per paragraph [0057] lines 1-4) having a first terminal (connection to balun input 21) and a selectively opened or closed second terminal (left of DC blocking circuit 30, switches are inherently known in the art to be opened or closed), the first terminal coupled to the first inductor node (as shown in Figs. 1 and 2);
a second switch (DC blocking circuit 40, includes adjustable capacitive network per paragraph [0056], which may consist of switches in series, per paragraph [0057] lines 1-4) having a third terminal (connection to balun input 22) and a selectively opened or closed fourth terminal (left of DC blocking circuit 40), the third terminal coupled to the second inductor node (as shown in Figs. 1 and 2);
a first amplifier (PA output 11, shown as a bipolar junction transistor) having a first input (11 base) and a first output (11 collector), the first output coupled to the selectively opened or closed second terminal of the first switch (11 base is connected left of DC blocking circuit 30); and
a second amplifier (PA output 12, shown as a bipolar junction transistor) having a second input (12 base) and a second output (12 collector), the second output coupled to the selectively opened or closed fourth terminal of the second switch (12 base is connected left of DC blocking circuit 40) wherein either amplifiers receiving a single-ended signal (RF signals transmitted as mentioned in paragraph [0042], per claims 11 and 16); and further comprising at least one of:
a first load (load-resonant circuit 73), configured as a first series combination of the second switch in an open state and the second LNA in an off state, coupled to the second inductor node, or
a second load (load-resonant circuit 72), configured as a second series combination of the first switch in the open state and the first LNA in the off state, coupled to the first inductor node (per claims 2, 12, and 17), wherein at least one of:
the first load is coupled to the second inductor node (load-resonant circuit 73 is connected to second balun input 22 via load balun 20) in response to the apparatus being configured to transform a single-ended input at the first LNA input to an amplified differential output across the first inductor node and the second inductor node, or
the second load is coupled to the first inductor node (load-resonant circuit 72 is connected to second balun input 21 via load balun 20) in response to the apparatus being configured to transform the single-ended input at the second LNA input to the amplified differential output across the first inductor node and the second inductor node (paragraph [0044], Load balun 20 is a balun arranged on the load line connected with push-pull PA 10, which realizes the connection between the balanced transmission line circuit and unbalanced transmission line circuit by converting matching input into differential output per claim 3); wherein
the load inductor, the first switch, the second switch, the first LNA, and the second LNA are components of a radio frequency front end (RFFE) (paragraph [0003] lines 3-5, RF front-end includes filter, LNA (Low Noise Amplifier), PA (Power Amplifier), switch and antenna tuning per claim 5), wherein the first switch, the second switch, the first LNA, and the second LNA are fabricated as a single core circuit (paragraph [0003] lines 3-5, RF front-end includes filter, LNA (Low Noise Amplifier), PA (Power Amplifier), switch and antenna tuning. PA is the core active device of RF front-end, per claim 8).
However, Hu does not explicitly teach one or more memories and one or more processors being configured to, individually or collectively, based at least in part on information stored in the one or more memories, and the first and second amplifiers are low noise amplifiers (LNA) are duplicates, wherein an external LNA (xLNA) having an xLNA input and an xLNA output, the xLNA separate from the RFFE, the xLNA output coupled to the second LNA input, and wherein a polarity of the first inductor node relative to the center inductor node is opposite to the polarity of the second inductor node relative to the center inductor node, and wherein the first LNA and the second LNA are a first plurality of LNAs and a second plurality of LNAs, respectively, and the apparatus is further configured to at least one of:
select one of the first plurality of LNAs to be the first LNA and turn off all other ones of the first plurality of LNAs, or select one of the second plurality of LNAs to be the second LNA and turn off all other ones of the second plurality of LNAs.
Lee teaches:
one or more memories (Fig. 13, memory 1318, per claim 16) and one or more processors being configured to, individually or collectively, based at least in part on information stored in the one or more memories (Control circuitry can include one or more processors per column 19 lines 22-34) and a first and second low noise amplifiers (Figs. 2 and 3, power amplifiers 220/320 and 230/330 of amplification system 200/300 which can be the same to amplifier assembly 160 per column 7 lines 43-45, wherein the amplifier may be low noise amplifiers per column 5, lines 25-35), an external LNA (Fig. 11C, per column 15 lines 43-48), wherein a polarity of the first inductor node relative to the center inductor node is opposite to the polarity of the second inductor node relative to the center inductor node (column 9 lines 11-13, the first portion 381 and the second portion 382 of the first coil 380 can include different characteristics), and wherein the first LNA and the second LNA are a first plurality of LNAs and a second plurality of LNAs, respectively (Fig. 13, PA module 1306, can include a plurality of power amplifiers per column 16 lines 64-66), each of the first plurality of LNAs and the second plurality of LNAs having a corresponding plurality of distinct gains (per column 3, line 4-21), and the apparatus is further configured to at least one of:
select one of the first plurality of LNAs to be the first LNA and turn off all other ones of the first plurality of LNAs, or select one of the second plurality of LNAs to be the second LNA and turn off all other ones of the second plurality of LNAs (column 3, line 4-21, switches are configured to be selected for operation of a variable-gain system).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have replaced the amplifier in Hu with the low noise amplifiers taught by Lee (Figs. 1-3) to generate a pair of amplified signals/signal components (per column 5 lines 25-35), thereby suggesting the obviousness of such a combination. Furthermore, it would be obvious for the amplifier taught by Lee to be duplicates as any number of amplification paths can be implemented (per column 8 lines 40-50). It would be further obvious to include a memory and processor, as taught by Lee to execute one or more instructions to thereby perform one or more operations to implement various functionality and store executable instructions (per column 19 lines 7-34), thereby suggesting the obviousness of such a combination. Furthermore it would be obvious to include an external LNA such as the amplifier taught by Lee (Fig. 11C) to implement multiple stages such as a driver stage and an output stage (per column 15 lines 43-48), thereby suggesting such a combination. It would be further obvious for the inductor taught by Hu (Figs. 1 and 2) to have different polarities as taught by Lee (column 9 lines 7-13) to provide different gain modes (per column 6 lines 25-27), thereby suggesting such a modification. Furthermore, it would be obvious for the amplifier system of Hu to correspond a plurality of distinct gains and be configured to select a plurality of LNAs as taught by Lee (column 3, line 4-21), thereby suggesting the obviousness of such a configuration.
Allowable Subject Matter
Claims 4, 6, 13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4, 6, 13, and 18:
the cited prior art of record, Hu (US 20220321066 A1, cited by the applicant), either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
“an internal transmit/receive switch coupled in parallel between the power amplifier balun and the first LNA input”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights