Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4, 15, 21 are objected to because of the following informalities:
Claim 4, the recited “NN” should be spelled out. For the record, it will be construed as “neural network” consistent with the disclosed detailed specification;’
Claims 15 and 21, the recited “OCT” should be spelled out.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-13, 15, 17-18, 20-21, 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP-2017111062-A, hereinafter “JP062”.
JP062 discloses the following as claimed (Fig.5 i.e., an IC system for OCT) and supporting disclosure (cited below):
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Regarding claim 1, An integrated electronic system for optical coherence tomography (OCT), the integrated electronic system comprising: an integrated circuit (IC) configured to generate image data based on OCT signals for display (Fig. 5 above; par. 0003),the IC comprising: an analog circuit configured to receive and digitize the OCT signals to generate digitized signals (514); a core processing subsystem configured to generate the image data based on the digitized signals (516); and a backend processing subsystem configured to receive and cause the image data (507 and par. 0049 i.e. photodetector and its drive/amplification/molding/output circuits) for display to a user (516). (For additional details, see also pars. 0017-18, 0020, 0048-0052).
Regarding claim 2, The integrated electronic system of claim 1, wherein the core processing subsystem comprises a model or a linearization circuit configured to linearize the digitized signals to generate linearized interference signals (Fig. 5, 506, 511-512; pars.0049-0052; Note: “model” is not considered due to “either/or” condition as claimed).
Regarding claim 4, The integrated electronic system of claim 2, wherein the core processing subsystem comprises a reconstruction pipeline configured to reconstruct the linearized interference signals to generate the image data using a reconstruction circuit or a NN (see rejection in claim 1 wrt to core processing subsystem; Note: NN is not considered because of “either/or” condition).
Regarding claim 5, The integrated electronic system of claim 1, wherein the backend processing subsystem comprises a first path and a second path that are configured to receive and cause the image data for display to the user, and wherein the first path has a lower latency compared to the second path (508-509; pars 0049-0052).
Regarding claim 6, The integrated electronic system of claim 1, wherein: the analog circuit comprises a plurality of analog to digital converters (ADCs) configured to digitize the OCT signals to generate digitized signals; and the core processing subsystem is configured to generate, depending on an application associated with the integrated electronic system, a control signal to reconfigure the plurality of ADCs (514, 515; Note: 514 is a DAQ board implying multiple ADCs; 515 is DSP for reconfiguration of ADC outputs resulting in tomographic image. See pars. 0052 for details).
Regarding claim 7, The integrated electronic system of claim 6, further comprising a printed circuit board (PCB), wherein the IC and a plurality of peripheral components are deployed on the PCB (Rejections of claims 1 and 6 are incorporated herein. See also par. 0003 i.e., SS-OCT integrated on a semiconductor substrate).
Regarding claim 8, The integrated electronic system of claim 7, wherein the core processing subsystem is configured to generate a plurality of control signals to control the plurality of peripheral components (See rejections of claims 1 and 4, which are fully incorporated herein).
Regarding claim 9, The integrated electronic system of claim 8, wherein the analog circuit comprises a plurality of digital to analog converters (DACs) configured to convert the plurality of control signals to a plurality of analog signals to control the plurality of peripheral components (See rejections of claims 1 and 6, which are fully incorporated herein).
Regarding claim 10, The integrated electronic system of claim 8, wherein at least two of the plurality of control signals is generated according to a single clock signal generated by the IC (See rejection of claim 5, which is incorporated herein; also 517 which outputs clock signals and par. 0049 for details).
Regarding claim 11, The integrated electronic system of claim 7, wherein the plurality of peripheral components comprise at least one optical sensor, at least one light source, a camera, at least one position sensor, at least one motor, or a beam-scanning assembly (Fig. 5: 1, 503, 507, 513; also pars. 0048-49 for details).
Regarding claim 12, The integrated electronic system of claim 6, wherein at least one of the plurality of ADCs is used to sample or record an a-line trigger signal (513 is used as trigger signal to DAQ board 514; see also par. 0049 for details).
Regarding claim 13, The integrated electronic system of claim 1, further comprising a graphics processing unit (GPU), and wherein the backend processing subsystem causes the image data to be transmitted to the GPU for processing and/or display to the user (Rejection of claim 1 is incorporated herein. See also Fig. 5, 515 serves as “backend” processing subsystem that transmits image signals to display 516 which inherently consists of GPU).
Regarding claim 15, which recites “A printed circuit assembly comprising: an optical detector configured to: receive one or more optical signals; and generate OCT interference signals based at least on the one or more optical signals; an integrated circuit (IC) configured to generate image data based on the OCT interference signals; and an image data interface configured to: receive the image data from the IC; and transmit the image data to an external device for display to a user.” (Rejection of claim 1 applies here. Note: integration on a semiconductor substrate disclosed in par. 0003 is the same as “a printed circuit assembly” as claimed).
Regarding claim 17, The printed circuit assembly of claim 15, wherein the IC comprises: an analog circuit configured to receive and digitize the OCT interference signals to generate digitized interference signals; a core processing subsystem configured to generate the image data based on the digitized interference signals; and a backend processing subsystem configured to: receive the image data from the core processing subsystem; and transmit the image data to the image data interface (Rejections of claims 1, 2, 6 and 15 are incorporated herein.
Regarding claim 18, The printed circuit assembly of claim 17, further comprising a plurality of peripheral components, and wherein the core processing subsystem is configured to control the plurality of peripheral components (See pars. 0020 , “The OCT according to the present embodiment may be provided with optical devices such as a fundus camera, a confocal laser scanning ophthalmoscope (SLO), and an anterior segment photographing machine”.).
Regarding claim 20, The printed circuit assembly of claim 15, wherein the one or more optical signals comprise an interferometric OCT signal or an interferometric k-clock signal (Fig. 5, 506; also par. 0039).
Regarding claim 21, An integrated circuit (IC) comprising: an analog circuit configured to receive and digitize OCT interference signals to generate digitized interference signals; a core processing subsystem configured to generate image data based on the digitized interference signals; and a backend processing subsystem configured to receive and cause the image data for display to a user (Rejection of claim 1 applies here).
Regarding claim 23, The integrated circuit of claim 21, wherein the backend processing subsystem comprises a first path and a second path that are configured to receive and transmit the image data to an image data interface, and wherein the first path has a lower latency compared to the second path (Rejection of claim 5 applies here).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 14, 16, 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over JP-2017111062-A, hereinafter “JP062” and further in view of US-20230184536-A1, hereinafter “McMorrow”.
Regarding claim 3, the rejection of claim 2 is incorporated herein. JP062 teaches a linearization circuit configured to linearize the digitized signals to generate linearized interference signals including k-clock signal, OCT interference signal, and variations of the k-clock signal (Fig. 5, 506, 511-512; pars.0016, 0039, 0049-0052), but does not teach using a neural network model or a machine learning model that is trained on using a dataset said signals. McMorrow teaches training AI engine based on learning statistics of SFE OCT to synchronize trigger clock (Figs. 12-13, pars. 0060-62).
It would have been obvious to one of ordinary skill in the art at the time of effective filing date to incorporate the teaching of McMorrow into JP062 in order to handle scanned images that may have adjustments due to phase errors or “mis-aligned” image sets to improve clock trigger synchronization.
Regarding claim 14, McMorrow in the combination further teaches The integrated electronic system of claim 13, wherein the GPU is used as an inference device that is disposed within the IC or outside the IC (Fig. 16, pars. 0069, 0075, “graphic processor unit” of graphic card connected via interface bus of which could be AI-based implementation i.e., as an inference device).
Regarding claim 16, McMorrow in the combination further teaches The printed circuit assembly of claim 15, wherein the image data interface is a Thunderbolt port, a DisplayPort connector, an OCuLink connector, a Universal Serial Bus (USB) port, a High-Definition Multimedia Interface (HDMI) port, an Ethernet connector, or a Peripheral Component Interconnect Express (PCIe) connector (Fig. 16, “Interface Bus”).
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Regarding claim 19, McMorrow in the combination further teaches The printed circuit assembly of claim 15, wherein the external device is a laptop, a computer workstation, a discrete graphics card, or a mobile device (See rejection of claim 14; par. 0069).
Regarding claim 22, McMorrow in the combination further teaches The integrated circuit of claim 21, wherein the core processing subsystem comprises a model configured to process the digitized interference signals to generate processed interference signals, wherein the model is a neural network model or a machine learning model (Rejections of claims 3 and 14 apply here).
Contact Information
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/VU LE/Supervisory Patent Examiner, Art Unit 2668
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