DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
In claim 12, at line 4: the term “for” is objected to because it typically indicates intended use and not present ability. The term should be replaced with “configured to”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1, 2, 3, 5, 12, 13, 14, 15, and 16, the phrase “optimal representations” is a relative phrase that renders the claims indefinite. There are no claim level criteria defining what makes a representation “optimal” so that the claimed comparison can be evaluated.
In claims 4 and 15, the phrase “preferentially ensure” is relative phrase with no threshold, metric, or condition. It is unclear how much reduction qualifies as “preferential”.
Claims 2-11 and 13-20 are rejected for their dependency on rejected base claims 1 and 12, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7. 12, 13, 15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub. No. 2005/0100802 to Callan et al. (“Callan”).
As to independent claim 12 and similarly recited independent claim 1, a non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate (¶ 0008: CRM and methods executed by a computer to perform OPC.), the program comprising sets of instructions for: generating, based on a first mask layout, a simulated wafer image comprising representations of IC components that are predicted to be manufactured for a first layer of the IC based on a received mask layout for the first layer (¶ 0006, 0008. Lithography simulators have traditionally used aerial image contours and simulated aerial images are used to predict the wafer results. The composite image in Callan is generated by performing imaging of the first mask and overlaying the second mask image onto the first mask image.); and comparing the simulated wafer image to a target wafer image comprising optimal representations of the IC components for the first layer (¶ 0008. Comparing an overlay image map area (simulated result) to a virtual target mask area (optimal representation).), said comparison using data regarding locations of components in at least one additional layer that interact with components in the first layer (¶ 0008. Callan generates the virtual target mask using design rules at least partially defining the relationship between the first mask and the second mask. The composite aerial image itself is formed by overlaying the second mask image onto the first.); and based on the comparison, modifying the first mask layout to generate a modified second mask layout for the first layer (¶ 0033. If the comparison determines the overlay is out of tolerance, corrective action is taken.).
As to claim 13 and similarly recited claim 2, the non-transitory machine-readable medium of claim 12, wherein comparing the simulated wafer image to the target wafer image comprises quantifying differences between the predicted manufactured representations and corresponding optimal representations of IC components (¶ 0035. The area of the overlay image maps may be calculated and compared to the area of the derived virtual target mask.).
As to claim 15 and similarly recited claim 4, the non-transitory machine-readable medium of claim 12, wherein modifying the first mask layout comprises modifying the mask layout to preferentially ensure that differences between the predicted manufactured representations and corresponding optimal representations of IC components that interact with components in at least one additional layer are reduced (¶ 0007, 0033. Callan inspects and refines multi-layer overlay quality. The virtual target mask is derived specifically from design rules defining the relationship (interaction) between layers.).
As to claim 18 and similarly recited claim 7, the non-transitory machine-readable medium of claim 12 further comprising identifying the data regarding locations of components in at least one additional layer by determining portions of the components that are intended to overlap with portions of components in at least one additional layer for proper functioning of the IC (¶ 0029, 0032. Callan generates the overlay image map using Boolean operators on the mask images. Boolean “AND” operation determines portions intended to overlap.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 6, 8-11, 14, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Callan in view of US Patent No. 8,512,919 to Fujimura et al. (“Fujimura”).
Callan teaches all the limitations of claims 1 and 12 from which claims 3, 5, 6, 8- 11, 14, 16, 17, 19, and 20 depend. Specifically, Callan teaches method and CRM for mask layout optimization including generating a simulated wafer image, comparing them to a target, and modifying the mask layout based on multi-layer interactions.
Callan fails to explicitly teach pixel-based comparison and weighting (claims 8, 10, 19) and weighted prioritization of interacting components (claims 3, 5, 14, 16). (Claims 6, 9, 11, 17, and 20 depend from 5, 8, 10, 16, and 19, respectively.)
Fujimura teaches a system for pixel-based mask optimization (Inverse Lithography Technology) that remedies these deficiencies. Fujimura teaches:
Optimizing the mask by performing a simulation of the wafer image and comparing it to a target wafer image. One of ordinary skill understands a wafer image is inherently a grid or pixel-based representation of the intensity or resist thresholds on the substrate. The result of such comparison is used as optimization criteria. (14:18-23).
Using the comparison result as optimization criteria. In image-based optimization, optimization criteria are a cost function inherently assigning value or importance to the difference between the simulated and target images (14:21-28).
It would have been obvious to one of ordinary skill in the art to combine Callan’s multi-layer interaction verification and mask correction with Fujimura’s optimization engine that utilizes pixel-by-pixel image comparison and weighted difference techniques. The combination achieves comparison on a pixel-by-pixel basis, and assigns greater weight to differences in more important pixels or regions.
Applying Fujimura to Callan would have predictably improved the accuracy and effectiveness of identifying and correcting overlay related errors, and would represent nothing more than the use of known techniques for their intended purpose.
As to claim 11, the method of claim 10, wherein pixels for representations of components that interact with components in at least one other layer are assigned higher weight values than pixels for representations of components that do not interact with components in any other layers (Callan identifies the overlay as the primary source of yield failure (¶ 0007). One of ordinary skill in the art would be motivated to prioritize these regions during Fujimura’s optimization by increasing the weight in the optimization criteria (14:18-28), such that the optimizer works harder to correct errors in these critical interacting regions compared to non-critical non-interacting regions.).
As to claim 17 and similarly recited claim 6, the non-transitory machine-readable medium of claim 16, wherein at least one IC component comprises a first region that interacts with a component in another layer of the IC and a second region that does not interact with any components in any other layer of the IC (Callan: ¶ 0028. Example of contact-to-metal design is provided. In a standard contact-to-metal design, a metal line connects to a contact. The part of the metal line touching the contact is the first region (interacting). The rest of the metal line, which runs to other parts of the circuit, is the second region that is not interacting with that specific contact.).
As to claim 20 and similarly recited claim 9, the non-transitory machine-readable medium of claim 19, wherein optimizing the mask layout for the first layer comprises modifying the mask layout with an objective of each pixel in the simulated wafer image matching the corresponding pixel in the target wafer image (Fujimura: 14:18-28. Minimizing the difference between two images in an optimization criteria is functionally identical to the claimed “objective of…matching”.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851