Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 05/21/2025, and 12/16/2025, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6 – 12, and 17 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Granik et al. (United States Patent Application Publication US20110004856A1), hereinafter referenced as Granik.
In regards to claim 1 (Granik) shows:
A method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components; Granik [0047] discusses computer system methodology for mask calculations, Granik [0059] teaches pixel-based inverse mask optimization formulation, and Granik [0142] addresses practical application to semiconductor manufacturing where these methods collectively establish mask layout optimization for IC fabrication.
the method comprising: iteratively generating a simulated wafer image comprising predicted manufactured shapes representing IC components for a layer of the IC based on a mask layout for the layer; Granik [0110] teaches objective function definition for image simulation, Granik [0112] details gradient descent optimization iterations, and Granik [0120] describes gradient calculation methods where these collectively establish iterative wafer image generation from mask layouts.
comparing the simulated wafer image to a target wafer image for the layer to determine whether the predicted manufactured shapes match corresponding shapes in the target wafer image; Granik [0066] teaches Euclidean distance comparison between target and actual images, Granik [0121] describes image fidelity error measurement, and Granik [0153] details optimization objectives for comparing predicted versus desired patterns.
performing an inverse lithography operation to adjust mask shapes of the mask layout based on the comparison; Granik [0059] establishes inverse lithography formulation, Granik [0112] teaches optimization algorithms including gradient descent, and Granik [0113] describes local variations methods where these collectively teach inverse lithography operations for mask adjustment.
wherein the inverse lithography operation explores different mask layouts; Granik [0112] teaches local variation algorithms comparing different transmission values, Granik [0113] describes exploratory pixel modifications, and Granik [0210] details constrained optimization methods that collectively demonstrate exploration of different mask configurations.
is biased to select mask shapes that ensure that critical regions of the predicted manufactured shapes more perfectly match the corresponding target shapes at expense of less important regions of the predicted manufactured shapes failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for pixel importance, Granik [0234] describes weight assignment based on feature significance, and Granik [0266] teaches adaptive weight adjustment methods that collectively establish biased selection favoring critical regions.
In regards to claim 6 (Granik) shows the method of claim 1:
wherein the inverse lithography operation adjusts mask shapes that relate to fabrication of the IC components; Granik [0112] teaches optimization routine modification of transmission characteristics, Granik [0113] describes mask pixel adjustment methods, and Granik [0156] addresses pattern optimization for semiconductor fabrication that collectively establish mask shape adjustment for IC component fabrication.
In regards to claim 7 (Granik) shows the method of claim 6:
wherein the inverse lithography operation further adds and removes mask shapes that relate to fabrication of the IC components; Granik [0042] introduces subresolution assist feature insertion, Granik [0055] teaches penalty functions for adding mask features, and Granik [0135] demonstrates assist feature insertion capability that collectively establish adding and removing mask shapes.
In regards to claim 8 (Granik) shows the method of claim 1:
Wherein the inverse lithography operation attempts to optimize an objective function; Granik [0110] teaches objective function definition that relates simulation of image intensity on wafer to pixel transmission characteristics and Granik [0112] describes optimization algorithms that minimize objective functions through iterative calculations.
the operation is biased by applying a greater cost in the objective function to the critical regions failing to match the corresponding target shapes than to the less important regions failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for objective function terms allowing differential importance assignment, Granik [0266] teaches adaptive weight adjustment that increases penalties for undesirable regions, Granik [0267] describes differential cost application methods, and Granik [0271] details weight modification procedures that collectively establish biased objective functions with greater costs for critical region failures.
In regards to claim 9 (Granik) shows the method of claim 8:
wherein the objective function is perfectly optimized when all of the predicted manufactured shapes exactly match all of the corresponding target shapes; Granik [0066] establishes optimization objective as Euclidean distance minimization and Granik [0153] teaches perfect optimization occurring when image intensity exactly matches ideal target with zero error difference.
In regards to claim 10 (Granik) shows the method of claim 9:
wherein a mask layout that perfectly optimizes the objective function does not exist; Granik [0084] discusses indefinite quadratic programming complexity with multiple minima and Granik [0157] teaches non-convex optimization problems where perfect global solutions may not exist due to fundamental mathematical limitations.
In regards to claim 11 (Granik) shows the method of claim 1:
wherein generating the simulated wafer image comprises simulating a set of lithography operations that are used to fabricate the layer of the IC using a set of masks based on the mask layout; Granik [0127] teaches electrical field caching for intensity calculations, Granik [0128] describes SOCS approximation for convolution operations, and Granik [0221] details computational methods for lithographic simulation that collectively establish simulation of lithography operations from mask to wafer.
In regards to claim 12 (Granik) shows:
A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components; Granik [0046] describes software implementation on computer readable storage medium and Granik [0047] teaches computer system execution of mask optimization calculations that collectively establish non-transitory medium storing optimization programs.
the program comprising sets of instructions for iteratively: generating a simulated wafer image comprising predicted manufactured shapes representing IC components for a layer of the IC based on a mask layout for the layer; Granik [0110] teaches objective function definition for image simulation, Granik [0112] details gradient descent optimization iterations, and Granik [0120] describes gradient calculation methods where these collectively establish iterative wafer image generation from mask layouts.
comparing the simulated wafer image to a target wafer image for the layer to determine whether the predicted manufactured shapes match corresponding shapes in the target wafer image; Granik [0066] teaches Euclidean distance comparison between target and actual images, Granik [0121] describes image fidelity error measurement, and Granik [0153] details optimization objectives for comparing predicted versus desired patterns.
performing an inverse lithography operation to adjust mask shapes of the mask layout based on the comparison; Granik [0059] establishes inverse lithography formulation, Granik [0112] teaches optimization algorithms including gradient descent, and Granik [0113] describes local variations methods where these collectively teach inverse lithography operations for mask adjustment.
wherein the inverse lithography operation explores different mask layouts; Granik [0112] teaches local variation algorithms comparing different transmission values, Granik [0113] describes exploratory pixel modifications, and Granik [0210] details constrained optimization methods that collectively demonstrate exploration of different mask configurations.
is biased to select mask shapes that ensure that critical regions of the predicted manufactured shapes more perfectly match the corresponding target shapes at expense of less important regions of the predicted manufactured shapes failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for pixel importance, Granik [0234] describes weight assignment based on feature significance, and Granik [0266] teaches adaptive weight adjustment methods that collectively establish biased selection favoring critical regions.
In regards to claim 17 (Granik) shows the method of claim 12:
wherein the inverse lithography operation adjusts mask shapes that relate to fabrication of the IC components; Granik [0112] teaches optimization routine modification of transmission characteristics, Granik [0113] describes mask pixel adjustment methods, and Granik [0156] addresses pattern optimization for semiconductor fabrication that collectively establish mask shape adjustment for IC component fabrication.
In regards to claim 18 (Granik) shows the method of claim 17:
wherein the inverse lithography operation further adds and removes mask shapes that relate to fabrication of the IC components; Granik [0042] introduces subresolution assist feature insertion, Granik [0055] teaches penalty functions for adding mask features, and Granik [0135] demonstrates assist feature insertion capability that collectively establish adding and removing mask shapes.
In regards to claim 19 (Granik) shows the method of claim 12:
Wherein the inverse lithography operation attempts to optimize an objective function; Granik [0110] teaches objective function definition that relates simulation of image intensity on wafer to pixel transmission characteristics and Granik [0112] describes optimization algorithms that minimize objective functions through iterative calculations.
the operation is biased by applying a greater cost in the objective function to the critical regions failing to match the corresponding target shapes than to the less important regions failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for objective function terms allowing differential importance assignment, Granik [0266] teaches adaptive weight adjustment that increases penalties for undesirable regions, Granik [0267] describes differential cost application methods, and Granik [0271] details weight modification procedures that collectively establish biased objective functions with greater costs for critical region failures.
In regards to claim 20 (Granik) shows the method of claim 19:
wherein the objective function is perfectly optimized when all of the predicted manufactured shapes exactly match all of the corresponding target shapes; Granik [0066] establishes optimization objective as Euclidean distance minimization and Granik [0153] teaches perfect optimization occurring when image intensity exactly matches ideal target with zero error difference.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 – 5, and 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over US20110004856A1 (Granik) as applied to claims 1 and 12 above, respectively, and in view of US20070037394A1 (Su).
In regards to claim 2 (Granik) does not show: wherein the critical regions of the predicted manufactured shapes represent regions of the IC components that form z-axis connections with IC components on other layers of the IC.
Su teaches wherein the critical regions of the predicted manufactured shapes represent regions of the IC components that form z-axis connections with IC components on other layers of the IC; Su [0052] describes multilayer interconnect architecture with vertical connections, Su [0054] details metal levels with orthogonal arrangements to minimize interference, and Su [0066] teaches intra-metal and inter-metal connections that collectively establish z-axis connections between IC layers.
The motivation to combine Granik and Su at the effective filing date of the invention is to apply established inverse lithography mask optimization techniques to the critical z-axis connection regions in multilayer IC structures, where accurate mask patterning is essential for proper via-to-metal electrical connectivity as both references address semiconductor manufacturing optimization challenges.
In regards to claim 3 (Granik) shows the method of claim 2:
wherein the less important regions of the predicted manufactured shapes represent regions of the IC components that do not form z-axis connections with any IC components on other layers; Granik [0051] introduces variable weighting functions for different pixel regions and Granik [0266] teaches differential weight assignment where pixels can receive lower importance values representing regions without critical connections.
In regards to claim 4 (Granik) does not show: wherein the layer of the IC is a metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in a neighboring dielectric layer.
Su teaches wherein the layer of the IC is a metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in a neighboring dielectric layer; Su [0052] describes metal interconnect layers within multilevel structures, Su [0064] teaches via connections between metal levels, and Su [0098] details via/metal enclosures that collectively establish metal wiring layers connected to vias in dielectric layers.
The motivation to combine Granik and Su at the effective filing date of the invention is to optimize mask layouts for metal wiring layers that connect to vias, since accurate patterning of metal-via interfaces is critical for device functionality and both references teach methods for improving semiconductor manufacturing processes through optimization techniques.
In regards to claim 5 (Granik) does not show: wherein the layer of the IC is a dielectric layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in neighboring metal wiring layers.
Su teaches wherein the layer of the IC is a dielectric layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in neighboring metal wiring layers; Su [0054] describes dielectric layer construction including ILD and IMD layers, Su [0121] teaches via formation through dielectric materials, and Su [0125] details dual damascene processes that collectively establish dielectric layers with vias connecting to metal wiring.
The motivation to combine Granik and Su at the effective filing date of the invention is to apply mask optimization methods to dielectric layers containing vias that connect to metal wiring, as proper via formation and metal connectivity are fundamental requirements in IC fabrication that benefit from improved lithographic accuracy as taught by both references.
In regards to claim 13 (Granik) does not show: wherein the critical regions of the predicted manufactured shapes represent regions of the IC components that form z-axis connections with IC components on other layers of the IC.
Su teaches wherein the critical regions of the predicted manufactured shapes represent regions of the IC components that form z-axis connections with IC components on other layers of the IC; Su [0052] describes multilayer interconnect architecture with vertical connections, Su [0054] details metal levels with orthogonal arrangements to minimize interference, and Su [0066] teaches intra-metal and inter-metal connections that collectively establish z-axis connections between IC layers.
The motivation to combine Granik and Su at the effective filing date of the invention is to apply established inverse lithography mask optimization techniques to the critical z-axis connection regions in multilayer IC structures, where accurate mask patterning is essential for proper via-to-metal electrical connectivity as both references address semiconductor manufacturing optimization challenges.
In regards to claim 14 (Granik) shows the method of claim 13:
wherein the less important regions of the predicted manufactured shapes represent regions of the IC components that do not form z-axis connections with any IC components on other layers; Granik [0051] introduces variable weighting functions for different pixel regions and Granik [0266] teaches differential weight assignment where pixels can receive lower importance values representing regions without critical connections.
In regards to claim 15 (Granik) does not show: wherein the layer of the IC is a metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in a neighboring dielectric layer.
Su teaches wherein the layer of the IC is a metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in a neighboring dielectric layer; Su [0052] describes metal interconnect layers within multilevel structures, Su [0064] teaches via connections between metal levels, and Su [0098] details via/metal enclosures that collectively establish metal wiring layers connected to vias in dielectric layers.
The motivation to combine Granik and Su at the effective filing date of the invention is to optimize mask layouts for metal wiring layers that connect to vias, since accurate patterning of metal-via interfaces is critical for device functionality and both references teach methods for improving semiconductor manufacturing processes through optimization techniques.
In regards to claim 16 (Granik) does not show: wherein the layer of the IC is a dielectric layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in neighboring metal wiring layers.
Su teaches wherein the layer of the IC is a dielectric layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in neighboring metal wiring layers; Su [0054] describes dielectric layer construction including ILD and IMD layers, Su [0121] teaches via formation through dielectric materials, and Su [0125] details dual damascene processes that collectively establish dielectric layers with vias connecting to metal wiring.
The motivation to combine Granik and Su at the effective filing date of the invention is to apply mask optimization methods to dielectric layers containing vias that connect to metal wiring, as proper via formation and metal connectivity are fundamental requirements in IC fabrication that benefit from improved lithographic accuracy as taught by both references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851