Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 04/30/2026, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 – 9, 11, 12, and 17 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over US20110004856A1 (Granik) in view of US20190137889A1 (Tel).
In regards to claim 1 (Granik) shows:
A method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components; Granik [0047] discusses computer system methodology for mask calculations, Granik [0059] teaches pixel-based inverse mask optimization formulation, and Granik [0142] addresses practical application to semiconductor manufacturing where these methods collectively establish mask layout optimization for IC fabrication.
the method comprising: iteratively generating a simulated first wafer image comprising predicted manufactured shapes representing IC components for a first layer of the IC based on a mask layout for the first layer; Granik [0211] teaches iterative comparison of exploratory pixel transmission values generating predicted manufactured shapes for different mask configurations, and Granik [0221] describes iterative recalculation of image intensity as mask pixels change that collectively establish iterative generation of simulated wafer images from mask layouts.
computing an objective function based on (i) comparing the simulated wafer image to a target second wafer image for the first layer to determine whether the predicted manufactured shapes match corresponding shapes in the target wafer image; Granik [0052] defines the objective function that relates a simulation of the image intensity on wafer to the pixel transmission characteristics of the mask data and the optics of the photolithographic printing system, Granik [0066] teaches Euclidean distance comparison between target and actual images, and Granik [0153] details optimization objectives for comparing predicted versus desired patterns.
performing an inverse lithography operation to adjust mask shapes of the mask layout based on optimizing the objective function; Granik [0059] establishes inverse lithography formulation, Granik [0112] teaches optimization algorithms including gradient descent, and Granik [0113] describes local variations methods where these collectively teach inverse lithography operations for mask adjustment.
wherein the inverse lithography operation explores different mask layouts; Granik [0112] teaches local variation algorithms comparing different transmission values, Granik [0113] describes exploratory pixel modifications, and Granik [0210] details constrained optimization methods that collectively demonstrate exploration of different mask configurations.
is biased by the objective function to select mask shapes that ensure that critical regions of the predicted manufactured shapes more perfectly match the corresponding target shapes at expense of less important regions of the predicted manufactured shapes failing to match the corresponding target shapes, said critical regions comprising the measured overlaps; Granik [0051] introduces weighting functions for pixel importance, Granik [0234] describes weight assignment based on feature significance, and Granik [0266] teaches adaptive weight adjustment methods that collectively establish biased selection favoring critical regions.
Granik differs from the claimed invention in that it does not explicitly disclose (ii) measuring overlaps between the predicted manufactured shapes in the simulated first wafer image and predicted manufactured shapes representing IC components for a second layer of the IC in a third wafer image for the second layer;
Tel teaches (ii) measuring overlaps between the predicted manufactured shapes in the simulated first wafer image and predicted manufactured shapes representing IC components for a second layer of the IC in a third wafer image for the second layer; Tel [0011] discloses that the interlayer characteristic is an overlapping area between a first pattern and a second pattern wherein the first pattern and the second pattern are in different layers on the substrate, Tel [0065] teaches that the overlapping area between pattern 5010 and pattern 5020 in different layers is an interlayer characteristic that may be simulated by simulating one or both patterns where the overlapping area equals a product of the overlapping widths of the two patterns, and Tel [0057] establishes that the cost function term f_p can be a function of an interlayer characteristic which is in turn a function of the design variables thereby incorporating the inter-layer overlap measurement into the objective function computation.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
In regards to claim 6 (Granik) shows the method of claim 1:
wherein the inverse lithography operation adjusts mask shapes that relate to fabrication of the IC components; Granik [0112] teaches optimization routine modification of transmission characteristics, Granik [0113] describes mask pixel adjustment methods, and Granik [0156] addresses pattern optimization for semiconductor fabrication that collectively establish mask shape adjustment for IC component fabrication.
In regards to claim 7 (Granik) shows the method of claim 6:
wherein the inverse lithography operation further adds and removes mask shapes that relate to fabrication of the IC components; Granik [0042] introduces subresolution assist feature insertion, Granik [0055] teaches penalty functions for adding mask features, and Granik [0135] demonstrates assist feature insertion capability that collectively establish adding and removing mask shapes.
In regards to claim 8 (Granik) shows the method of claim 1:
Wherein the inverse lithography operation is biased by applying a greater cost in the objective function to the critical regions failing to match the corresponding target shapes than to the less important regions failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for objective function terms allowing differential importance assignment, Granik [0266] teaches adaptive weight adjustment that increases penalties for undesirable regions, Granik [0267] teaches adaptive modification of weight values during the optimization process, and Granik [0271] details weight modification procedures that collectively establish biased objective functions with greater costs for critical region failures.
In regards to claim 9 (Granik) shows the method of claim 8:
wherein the objective function is perfectly optimized when all of the predicted manufactured shapes exactly match all of the corresponding target shapes; Granik [0066] establishes optimization objective as Euclidean distance minimization and Granik [0153] teaches perfect optimization occurring when image intensity exactly matches ideal target with zero error difference.
In regards to claim 11 (Granik) shows the method of claim 1:
wherein generating the simulated wafer image comprises simulating a set of lithography operations that are used to fabricate the layer of the IC using a set of masks based on the mask layout; Granik [0127] teaches electrical field caching for intensity calculations, Granik [0128] describes SOCS approximation for convolution operations, and Granik [0221] details computational methods for lithographic simulation that collectively establish simulation of lithography operations from mask to wafer.
In regards to claim 12 (Granik) shows:
A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components; Granik [0046] describes software implementation on computer readable storage medium and Granik [0047] teaches computer system execution of mask optimization calculations that collectively establish non-transitory medium storing optimization programs.
the program comprising sets of instructions for: iteratively generating a simulated first wafer image comprising predicted manufactured shapes representing IC components for a first layer of the IC based on a mask layout for the first layer; Granik [0211] teaches iterative comparison of exploratory pixel transmission values generating predicted manufactured shapes for different mask configurations, and Granik [0221] describes iterative recalculation of image intensity as mask pixels change that collectively establish iterative generation of simulated wafer images from mask layouts.
computing an objective function based on (i) comparing the simulated wafer image to a target second wafer image for the first layer to determine whether the predicted manufactured shapes match corresponding shapes in the target wafer image; Granik [0052] defines the objective function that relates a simulation of the image intensity on wafer to the pixel transmission characteristics of the mask data and the optics of the photolithographic printing system, Granik [0066] teaches Euclidean distance comparison between target and actual images, and Granik [0153] details optimization objectives for comparing predicted versus desired patterns.
performing an inverse lithography operation to adjust mask shapes of the mask layout based on optimizing the objective function; Granik [0059] establishes inverse lithography formulation, Granik [0112] teaches optimization algorithms including gradient descent, and Granik [0113] describes local variations methods where these collectively teach inverse lithography operations for mask adjustment.
wherein the inverse lithography operation explores different mask layouts; Granik [0112] teaches local variation algorithms comparing different transmission values, Granik [0113] describes exploratory pixel modifications, and Granik [0210] details constrained optimization methods that collectively demonstrate exploration of different mask configurations.
is biased by the objective function to select mask shapes that ensure that critical regions of the predicted manufactured shapes more perfectly match the corresponding target shapes at expense of less important regions of the predicted manufactured shapes failing to match the corresponding target shapes, said critical regions comprising the measured overlaps; Granik [0051] introduces weighting functions for pixel importance, Granik [0234] describes weight assignment based on feature significance, and Granik [0266] teaches adaptive weight adjustment methods that collectively establish biased selection favoring critical regions.
Granik differs from the claimed invention in that it does not explicitly disclose (ii) measuring overlaps between the predicted manufactured shapes in the simulated first wafer image and predicted manufactured shapes representing IC components for a second layer of the IC in a third wafer image for the second layer;
Tel teaches (ii) measuring overlaps between the predicted manufactured shapes in the simulated first wafer image and predicted manufactured shapes representing IC components for a second layer of the IC in a third wafer image for the second layer; Tel [0011] discloses that the interlayer characteristic is an overlapping area between a first pattern and a second pattern wherein the first pattern and the second pattern are in different layers on the substrate, Tel [0065] teaches that the overlapping area between pattern 5010 and pattern 5020 in different layers is an interlayer characteristic that may be simulated by simulating one or both patterns where the overlapping area equals a product of the overlapping widths of the two patterns, and Tel [0057] establishes that the cost function term f_p can be a function of an interlayer characteristic which is in turn a function of the design variables thereby incorporating the inter-layer overlap measurement into the objective function computation.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
In regards to claim 17 (Granik) shows the non-transitory machine-readable medium of claim 12:
wherein the inverse lithography operation adjusts mask shapes that relate to fabrication of the IC components; Granik [0112] teaches optimization routine modification of transmission characteristics, Granik [0113] describes mask pixel adjustment methods, and Granik [0156] addresses pattern optimization for semiconductor fabrication that collectively establish mask shape adjustment for IC component fabrication.
In regards to claim 18 (Granik) shows the non-transitory machine-readable medium of claim 17:
wherein the inverse lithography operation further adds and removes mask shapes that relate to fabrication of the IC components; Granik [0042] introduces subresolution assist feature insertion, Granik [0055] teaches penalty functions for adding mask features, and Granik [0135] demonstrates assist feature insertion capability that collectively establish adding and removing mask shapes.
In regards to claim 19 (Granik) shows the non-transitory machine-readable medium of claim 12:
Wherein the inverse lithography operation is biased by applying a greater cost in the objective function to the critical regions failing to match the corresponding target shapes than to the less important regions failing to match the corresponding target shapes; Granik [0051] introduces weighting functions for objective function terms allowing differential importance assignment, Granik [0266] teaches adaptive weight adjustment that increases penalties for undesirable regions, Granik [0267] teaches adaptive modification of weight values during the optimization process, and Granik [0271] details weight modification procedures that collectively establish biased objective functions with greater costs for critical region failures.
In regards to claim 20 (Granik) shows the non-transitory machine-readable medium of claim 19:
wherein the objective function is perfectly optimized when all of the predicted manufactured shapes exactly match all of the corresponding target shapes; Granik [0066] establishes optimization objective as Euclidean distance minimization and Granik [0153] teaches perfect optimization occurring when image intensity exactly matches ideal target with zero error difference.
In regards to claim 21 (Granik) does not show: wherein the inverse lithography operation is further biased by applying a cost based on measurement of the overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image;
Tel teaches wherein the inverse lithography operation is further biased by applying a cost based on measurement of the overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image; TEL [0011] discloses that the interlayer characteristic is an overlapping area between patterns in different layers on the substrate, TEL [0057] establishes that cost function terms f_p can be functions of interlayer characteristics with associated weight constants w_p such that the overlap measurement is incorporated as a cost term in the objective function, and TEL [0065] confirms that the overlapping area between simulated patterns in different layers constitutes the measured interlayer characteristic that is computed and weighted within the cost function, where this overlap-based cost term directly biases the optimization toward maintaining proper inter-layer overlap regions.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
Claims 2 – 5, and 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over US20110004856A1 (Granik) in view of US20190137889A1 (Tel) as applied to claims 1 and 12 above, respectively, and in view of US20070037394A1 (Su).
In regards to claim 2 (Granik modified by Tel) does not show: wherein measured overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image represent regions of the IC components that form z-axis connections with IC components on other layers of the IC.
Su teaches wherein measured overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image represent regions of the IC components that form z-axis connections with IC components on other layers of the IC; Su [0052] describes multilayer interconnect architecture with vertical connections, Su [0054] details metal levels with orthogonal arrangements to minimize interference, and Su [0066] teaches intra-metal and inter-metal connections that collectively establish z-axis connections between IC layers.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
In regards to claim 3 (Granik) shows the method of claim 2:
wherein the less important regions of the predicted manufactured shapes represent regions of the IC components that do not form z-axis connections with any IC components on other layers; Granik [0051] introduces variable weighting functions for different pixel regions and Granik [0266] teaches differential weight assignment where pixels can receive lower importance values representing regions without critical connections.
In regards to claim 4 (Granik modified by Tel) does not show: wherein the first layer of the IC is a metal wiring layer and the second layer is a neighboring dielectric layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in the neighboring dielectric layer.
Su teaches wherein the first layer of the IC is a metal wiring layer and the second layer is a neighboring dielectric layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in the neighboring dielectric layer; Su [0052] describes metal interconnect layers within multilevel structures, Su [0064] teaches via connections between metal levels, and Su [0098] details via/metal enclosures that collectively establish metal wiring layers connected to vias in dielectric layers.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
In regards to claim 5 (Granik modified by Tel) does not show: wherein the first layer of the IC is a dielectric layer and the second layer is a neighboring metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in the neighboring metal wiring layer.
Su teaches wherein the first layer of the IC is a dielectric layer and the second layer is a neighboring metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in the neighboring metal wiring layer; Su [0054] describes dielectric layer construction including ILD and IMD layers, Su [0121] teaches via formation through dielectric materials, and Su [0125] details dual damascene processes that collectively establish dielectric layers with vias connecting to metal wiring.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
In regards to claim 13 (Granik modified by Tel) does not show: wherein measured overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image represent regions of the IC components that form z-axis connections with IC components on other layers of the IC.
Su teaches wherein measured overlaps between the predicted manufactured shapes in the simulated first wafer image and the predicted manufactured shapes in the third wafer image represent regions of the IC components that form z-axis connections with IC components on other layers of the IC; Su [0052] describes multilayer interconnect architecture with vertical connections, Su [0054] details metal levels with orthogonal arrangements to minimize interference, and Su [0066] teaches intra-metal and inter-metal connections that collectively establish z-axis connections between IC layers.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
In regards to claim 14 (Granik) shows the non-transitory machine-readable medium of claim 13:
wherein the less important regions of the predicted manufactured shapes represent regions of the IC components that do not form z-axis connections with any IC components on other layers; Granik [0051] introduces variable weighting functions for different pixel regions and Granik [0266] teaches differential weight assignment where pixels can receive lower importance values representing regions without critical connections.
In regards to claim 15 (Granik modified by Tel) does not show: wherein the first layer of the IC is a metal wiring layer and the second layer is a neighboring dielectric layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in the neighboring dielectric layer.
Su teaches wherein the first layer of the IC is a metal wiring layer and the second layer is a neighboring dielectric layer, wherein at least a subset of the z-axis connections comprise connections between interconnect wire segments in the metal wiring layer and vias in the neighboring dielectric layer; Su [0052] describes metal interconnect layers within multilevel structures, Su [0064] teaches via connections between metal levels, and Su [0098] details via/metal enclosures that collectively establish metal wiring layers connected to vias in dielectric layers.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
In regards to claim 16 (Granik modified by Tel) does not show: wherein the first layer of the IC is a dielectric layer and the second layer is a neighboring metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in the neighboring metal wiring layer.
Su teaches wherein the first layer of the IC is a dielectric layer and the second layer is a neighboring metal wiring layer, wherein at least a subset of the z-axis connections comprise connections between vias in the dielectric layer and interconnect wire segments in the neighboring metal wiring layer; Su [0054] describes dielectric layer construction including ILD and IMD layers, Su [0121] teaches via formation through dielectric materials, and Su [0125] details dual damascene processes that collectively establish dielectric layers with vias connecting to metal wiring.
The motivation to combine Granik and Tel at the effective filing date of the invention is to improve inverse lithography mask optimization for multi-layer IC manufacturing by incorporating inter-layer overlap measurement into the ILT objective function, as TEL expressly recognizes that overlapping areas between patterns in different IC layers are critical interlayer characteristics warranting differential weighting in lithographic cost functions, and a person having ordinary skill in the art would have been motivated to incorporate TEL's interlayer overlap cost term into Granik's weighted ILT framework to achieve mask optimization that accounts for both intra-layer pattern fidelity and inter-layer overlay accuracy.
The motivation to combine Granik, Tel, and Su at the effective filing date of the invention is to apply the Granik-TEL inter-layer overlap optimization framework specifically to z-axis connection regions, as Su identifies vias and contacts between metal wiring and neighboring dielectric layers as the functionally critical inter-layer regions in BEOL IC manufacturing, and a person having ordinary skill in the art would have recognized these regions as the natural targets for the higher-weighted interlayer cost terms taught by TEL within Granik's ILT framework.
Response to Argument
Applicant's arguments filed on April 30, 2026 have been fully considered but they are not persuasive.
With respect to independent claims 1 and 12, Applicant argues that neither Granik nor Su discloses measuring overlaps between predicted manufactured shapes in different IC layers within an iterative inverse lithography process, and that Su teaches only interconnect architecture without mask simulation or overlap measurement capability. These arguments are acknowledged with respect to the original rejection over Granik in view of Su, which is hereby withdrawn. Granik is directed exclusively to single-layer inverse lithography optimization and does not teach the inter-layer overlap measurement introduced by amendment, and Su does not teach mask simulation or iterative overlap measurement within an ILT framework.
However, the claims remain unpatentable under 35 U.S.C. § 103 over the newly cited combination of Granik and US20190137889A1 (TEL et al.). TEL explicitly teaches that an interlayer characteristic is an overlapping area between a first pattern and a second pattern wherein the first pattern and the second pattern are in different layers on the substrate, and that such overlapping area may be simulated by simulating one or both patterns. TEL further teaches incorporating this interlayer overlap measurement as a weighted cost function term, where interlayer characteristics with narrower permitted ranges are given higher weight values. Applicant's argument that the prior art lacks inter-layer overlap measurement within a mask optimization cost function is therefore directly rebutted by TEL. A person having ordinary skill in the art would have found it obvious to incorporate TEL's interlayer overlap cost term into Granik's inverse lithography framework, as both references address lithographic optimization and TEL expressly recognizes interlayer overlap as a critical characteristic warranting differential weighting in multi-variable cost functions.
With respect to dependent claims 2 and 13, Applicant's argument that the prior art fails to identify the measured overlaps as representing z-axis connections between IC layers is not persuasive. Su explicitly teaches multilayer IC interconnect architecture wherein vias and contacts between metal wiring layers and neighboring dielectric layers constitute the functionally critical inter-layer regions. The combination of TEL's interlayer overlap measurement and Su's identification of z-axis connections as critical inter-layer regions renders claims 2 and 13 unpatentable. The remaining dependent claims are maintained for the reasons stated in the body of the rejection.
The remaining arguments with respect to claims 3, 6-9, 11, 14, 17-21 have been fully considered but are not persuasive for the reasons stated above. The rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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