Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 8/24/2024 and IDS filed on 5/21/2025 and 12/16/2025.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mukherjee et al. (U.S. Pub. No. 2007/0220476 A1).
As per claim 1, Mukherjee discloses:
A method for modifying a mask layout for producing masks used to manufacture an integrated circuit (IC), the mask layout comprising a plurality of mask images for a plurality of layers of the IC, the method comprising:
identifying a first set of mask images corresponding to a first layer of the design layout and a second set of mask images corresponding to a second layer of the design layout (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Figure 7, i.e. 801 – provide circuit design including mask shapes for all layers);
formulating a problem that expresses correlation between desired shapes of IC components and predicted as-manufactured shapes of the IC components that are produced through wafer simulation operations (See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration, See Figure 7, i.e. 805 & 806 & 811 – simulate initial image for all layers, See Para [0054]-[0055], i.e. simulated images…compared to an appropriate set of target images),
wherein the IC components comprise a plurality of components on the first layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers ) and a plurality of vias on the second layer, each via connecting a component on the first layer to a component on another layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects);
and iteratively solving the problem by iteratively exploring modifications to both the first and second sets of mask images in order to identify modified first and second sets of mask images that result in predicted as-manufactured shapes for the plurality of components on the first layer and the plurality of vias on the second layer that sufficiently correlate to the desired shapes on the plurality of components and plurality of vias (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 2, Mukherjee discloses all of the features of claim 1 as discloses above wherein Mukherjee also discloses identifying a third set of mask images corresponding to a third layer of the design layout, wherein: the plurality of components on the first layer is a first plurality of components; the IC components further comprise a second plurality of components on a third layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Figure 7, i.e. 801 – provide circuit design including mask shapes for all layers); each via of a set of the vias connects a first-layer component to a third-layer component (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects); and iteratively solving the problem comprises exploring modifications to the first, second, and third sets of mask images in order to identify modified first and second sets of mask images that result in predicted as-manufactured shapes for the plurality of components and the plurality of vias that sufficiently correlate to the desired shapes on the pluralities of components and plurality of vias (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 3, Mukherjee discloses all of the features of claim 2 as discloses above wherein Mukherjee also discloses wherein the first and third layers are metal layers and the second layer is a dielectric layer between the first and third layers with vias connecting components on the first layer and third layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects).
As per claim 4, Mukherjee discloses all of the features of claim 1 as discloses above wherein Mukherjee also discloses wherein the first set of mask images are used to fabricate a metal wiring first layer of the IC and the second set of mask images are used to fabricate vias of a dielectric second layer adjacent to the first layer (See Para [0004], i.e. each layer of metal is connected to the metal layer above by a via layer, See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape).
As per claim 5, Mukherjee discloses all of the features of claim 1 as discloses above wherein Mukherjee also discloses identifying a plurality of overlaps between components in the first layer and vias in the second layer, each respective overlap comprising a respective first-layer component and a respective via that connects the respective first-layer component to another component in another layer (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers).
As per claim 6, Mukherjee discloses all of the features of claim 5 as discloses above wherein Mukherjee also discloses wherein the formulated problem further expresses correlations between pairs of predicted as-manufactured shapes for each identified overlap (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration).
As per claim 7, Mukherjee discloses all of the features of claim 5 as discloses above wherein Mukherjee also discloses wherein the modified first and second sets of mask images optimize the identified overlaps (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration).
As per claim 8, Mukherjee discloses all of the features of claim 1 as discloses above wherein Mukherjee also discloses wherein iteratively solving the problem comprises, for a particular iteration: performing wafer simulation operations (i) to generate, from a current iteration of the first set of mask images, a first wafer image comprising predicted as-manufactured shapes of the plurality of components on the first layer and (ii) to generate, from a current iteration of the second set of mask images, a second wafer image comprising predicted as-manufactured shapes of the plurality of vias on the second layer (See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration); and modifying at least one mask image in the first set of mask images and at least one mask image in the second set of mask images (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 9, Mukherjee discloses all of the features of claim 8 as discloses above wherein Mukherjee also discloses wherein modifying at least one mask image in the first and second sets of mask images comprises: modifying a first mask shape in a first mask image of the first set of mask images, the first mask shape relating to fabrication of a first first-layer IC component; and modifying a second mask shape in a second mask image of the second set of mask images, the second mask shape relating to fabrication of a second-layer via that overlaps with a second first-layer IC component (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration, See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges).
As per claim 10, Mukherjee discloses all of the features of claim 9 as discloses above wherein Mukherjee also discloses wherein modifying the at least one mask image in the first and second sets of mask images further comprises modifying a third mask shape in the second mask image, the third mask shape relating to fabrication of a second-layer via that overlaps the first first-layer IC component (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges –[prior art modify all layers, therefore include modifying the third mask shape]).
As per claim 11, Mukherjee discloses all of the features of claim 9 as discloses above wherein Mukherjee also discloses wherein no mask shape relating to fabrication of the second first-layer IC component is modified (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify based on evaluation (Figure 7, i.e. 813), therefore would not modify mask shape of second first layer when it does not violate any design rule]).
As per claim 12, Mukherjee discloses:
A non-transitory machine-readable medium storing a program which when executed by at least one processing unit modifies a mask layout for producing masks used to manufacture an integrated circuit (IC), the mask layout comprising a plurality of mask images for a plurality of layers of the IC, the program comprising sets of instructions (See Figure 13 & Para [0060], i.e. central processing…computer readable) for:
identifying a first set of mask images corresponding to a first layer of the design layout and a second set of mask images corresponding to a second layer of the design layout (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Figure 7, i.e. 801 – provide circuit design including mask shapes for all layers);
formulating a problem that expresses correlation between desired shapes of IC components and predicted as-manufactured shapes of the IC components that are produced through wafer simulation operations (See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration, See Figure 7, i.e. 805 & 806 & 811 – simulate initial image for all layers, See Para [0054]-[0055], i.e. simulated images…compared to an appropriate set of target images), wherein the IC components comprise a plurality of components on the first layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers ) and a plurality of vias on the second layer, each via connecting a component on the first layer to a component on another layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects); and
iteratively solving the problem by iteratively exploring modifications to both the first and second sets of mask images in order to identify modified first and second sets of mask images that result in predicted as-manufactured shapes for the plurality of components on the first layer and the plurality of vias on the second layer that sufficiently correlate to the desired shapes on the plurality of components and plurality of vias (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 13, Mukherjee discloses all of the features of claim 12 as discloses above wherein Mukherjee also discloses identifying a third set of mask images corresponding to a third layer of the design layout, wherein: the plurality of components on the first layer is a first plurality of components; the IC components further comprise a second plurality of components on a third layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Figure 7, i.e. 801 – provide circuit design including mask shapes for all layers); each via of a set of the vias connects a first-layer component to a third-layer component (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects); and the set of instructions for iteratively solving the problem comprises a set of instructions for exploring modifications to the first, second, and third sets of mask images in order to identify modified first and second sets of mask images that result in predicted as-manufactured shapes for the plurality of components and the plurality of vias that sufficiently correlate to the desired shapes on the pluralities of components and plurality of vias (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 14, Mukherjee discloses all of the features of claim 13 as discloses above wherein Mukherjee also discloses wherein the first and third layers are metal layers and the second layer is a dielectric layer between the first and third layers with vias connecting components on the first layer and third layer (See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape, See Para [0004], i.e. connected by contact pads (CA) to several layers of metal interconnects).
As per claim 15, Mukherjee discloses all of the features of claim 12 as discloses above wherein Mukherjee also discloses wherein the first set of mask images are used to fabricate a metal wiring first layer of the IC and the second set of mask images are used to fabricate vias of a dielectric second layer adjacent to the first layer (See Para [0004], i.e. each layer of metal is connected to the metal layer above by a via layer, See Figure 2 and Figure 3, i.e. layer 1, layer2 , layer 3, See Para [0041]-[0042], i.e. three layers…Layer 1, Layer 2 and Layer 3, See Para [0051]-[0052], i.e. inputs…all mask shapes associated with the physical layers, See Claim 10, i.e. second layer…via shape).
As per claim 16, Mukherjee discloses all of the features of claim 12 as discloses above wherein Mukherjee also discloses wherein the program further comprises a set of instructions for identifying a plurality of overlaps between components in the first layer and vias in the second layer, each respective overlap comprising a respective first-layer component and a respective via that connects the respective first-layer component to another component in another layer (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers).
As per claim 17, Mukherjee discloses all of the features of claim 16 as discloses above wherein Mukherjee also discloses wherein the formulated problem further expresses correlations between pairs of predicted as-manufactured shapes for each identified overlap (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration).
As per claim 18, Mukherjee discloses all of the features of claim 16 as discloses above wherein Mukherjee also discloses wherein the modified first and second sets of mask images optimize the identified overlaps (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration).
As per claim 19, Mukherjee discloses all of the features of claim 12 as discloses above wherein Mukherjee also discloses wherein the set of instructions for iteratively solving the problem comprises sets of instructions for, for a particular iteration: performing wafer simulation operations (i) to generate, from a current iteration of the first set of mask images, a first wafer image comprising predicted as-manufactured shapes of the plurality of components on the first layer and (ii) to generate, from a current iteration of the second set of mask images, a second wafer image comprising predicted as-manufactured shapes of the plurality of vias on the second layer (See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration); and modifying at least one mask image in the first set of mask images and at least one mask image in the second set of mask images (See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges, See Para [0044]-[0050] –[prior art modify all layers through simulation in order to meet OPC requirement is considered as the iteratively solving as cited above]).
As per claim 20, Mukherjee discloses all of the features of claim 19 as discloses above wherein Mukherjee also discloses wherein the set of instructions for modifying at least one mask image in the first and second sets of mask images comprises sets of instructions for: modifying a first mask shape in a first mask image of the first set of mask images, the first mask shape relating to fabrication of a first first-layer IC component; and modifying a second mask shape in a second mask image of the second set of mask images, the second mask shape relating to fabrication of a second-layer via that overlaps with a second first-layer IC component (See Para [0008]-[0010], i.e. each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria, See Para [0048]-[0050], i.e. overlaying of shapes…interacting layers, See Para [0051]-[0053], i.e. each layer is associated with corresponding models for simulation…lithography process model…simulated images…for each layer I…OPC iteration, See Figure 7, i.e. 815 – modify fragment … modified image – 818 – Converged, See Para [0054]-[0056], i.e. fragment … is modified … until OPC converges).
Conclusion
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851