Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 6/8/2026 in response to the Office action dated 3/6/2026. Claims 1-3, 6, 11, 14, 17, and 20-21 have been amended. Claims 1-6 and 8-21 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-21 are rejected under 35 U.S.C. 103 as being unpatentable over Desai et al. (US 20200081830 A1), hereinafter Desai, in view of Liu et al. (US 20140325141 A1), hereinafter Liu, and further in view of Ben Dayan et al. (US 20200004725 A1), hereinafter Ben Dayan.
Regarding claim 1, Desai teaches a method comprising: receiving from a host device, at a circuit of a device configured as memory, using a memory access protocol as a first protocol, a request to make a region of memory allocatable (Paragraphs 22-24; Fig. 1, solid-state drive SSD 101, using the NVMExpress [first] protocol, receives a deallocate command from host 102 at controller 103 [circuit] specifying address ranges),
the request comprising a memory address range and an operation indicator indicating the request to make the region of memory allocatable (Paragraphs 17, 22, the deallocate command includes an LBA range (the command also includes an indication that it is a deallocate command to distinguish it from other commands));
determining that the circuit has received the request to make the region of memory allocatable, wherein the determining comprises polling the circuit for the request (Paragraphs 22, 24-25; Fig. 1, sending a response to [polling] front end module 106 via flash translation layer 108 [circuit] following receiving the deallocate command targeting LBA ranges in SSD 101 at flash translation layer 108).
Desai does not explicitly teach expansion memory and making, using a second protocol, the region of memory allocatable based on determining that the circuit has received the request; and performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from making the region of memory allocatable.
However, Liu teaches an expansion memory (Paragraph 16; Fig. 1, multiple connectable storage systems 191, 192), and
making, using a second protocol, the region of memory allocatable based on determining that the circuit has received the request (Paragraph 25; Fig. 2, upon receiving a SATA TRIM command [request] targeting file blocks [region of memory] at VAHCI 173, translating a SATA TRIM command into a SCSI [second protocol] UNMAP command which subsequently deletes [makes allocatable] the targeted file blocks).
Desai and Liu are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Desai to further include the expansion memory and the processing of the request using a second protocol according to the teachings of Liu. The motivation for doing so would have been to increase memory capacity, increase compatibility between different protocols, and decrease data fragmentation (Liu, Paragraphs 4-5).
Desai in view of Liu does not explicitly teach performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from making the region of memory allocatable.
However, Ben Dayan teaches performing a garbage collection operation as a background process (Paragraph 49, SSDs may run a background garbage collection process),
wherein the garbage collection operation is performed as a separate operation from making the region of memory allocatable (Paragraphs 49, 51-52, SSDs may run the garbage collection in the background following the processing of a trim/deallocate command).
Desai, Liu, and Ben Dayan are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Desai in view of Liu to further include the background garbage collection process according to the teachings of Ben Dayan. The motivation for doing so would have been to ensure consistently low latency times (Ben Dayan, Paragraph 50).
Regarding claim 2, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein making the region of memory allocatable comprises: making allocatable at least a portion of storage media of the device corresponding to the region of memory (Desai, Paragraphs 24-25; Fig. 1, updating L2P mapping table 122 to deallocate the corresponding physical addresses [portion of storage] of non-volatile memory 114).
Regarding claim 3, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein making the region of memory allocatable comprises: assigning a value to at least a portion of storage media of the device corresponding to the region of memory (Desai, Paragraph 39; Fig. 4, the deallocation request is converted to a write zeroes command, wherein the corresponding memory portions are set to [assigned] ‘0’).
Regarding claim 4, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein the circuit of the device is a first circuit (Desai, Paragraph 21; Fig. 1, flash translation layer 108);
the device comprises a second circuit, the at least one circuit configured to track allocated addresses on the device (Desai, Paragraph 25; Fig. 1, address translation hardware accelerator 120 [second circuit] utilizes L2P mapping table 122 to map [track] written addresses); and the method further comprises:
modifying the second circuit to make addresses allocatable corresponding to the region of memory (Desai, Paragraph 25; Fig. 1, address translation hardware accelerator 120 utilizes L2P mapping table 122 to deallocate the specified address ranges).
Regarding claim 5, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, further comprising: modifying the device to indicate that the region of memory is allocatable (Desai, Paragraph 25; Fig. 1, updating bitmap 116 of SSD 101 [device] to indicate addresses that have been deallocated);
and adding the region of memory to a list of allocatable memory locations (Desai, Paragraph 24; Figs. 1 and 3, flash translation layer 108 copies the memory range and offset of the deallocate command to an entry in trim table [list] 124).
Regarding claim 6, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein making the region of memory allocatable comprises: sending, based on receiving the request, a command to the circuit to make the region of memory allocatable (Desai, Paragraphs 22, 24; Fig. 1, front end module 106 receives a deallocation command including a specified address range and transmits the command to flash translation layer 108).
Regarding claim 8, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein the operation indicator comprises at least one of: a trim operation, an initialize operation, a de-allocate operation (Desai, Paragraph 22, deallocate command),
an initialize operation, a flush operation, a persist operation, a prefetch operation, an evict operation, an encrypt operation, a compress operation, and a de-duplication operation.
Regarding claim 9, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein the operation indicator comprises a command to perform at least one of: assigning a value to at least a portion of storage media of the device corresponding to the memory address range (Desai, Paragraph 39; Fig. 4, the deallocate command is converted to a write zeroes command, wherein the corresponding memory portions/address ranges are set to 0) and
making at least a portion of the storage media of the device corresponding to the memory range address allocatable (Desai, Paragraph 39; Fig. 4, setting the memory locations to 0 deallocates the corresponding address range portions of the non-volatile memory).
Regarding claim 10, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, further comprising: sending a completion message comprising at least one of: an indicator that the memory address range has been assigned a value and an indicator that the memory address range is allocatable (Desai, Paragraph 25; Fig. 1, sending a deallocate completion status to the host 102 indicating that the specified address ranges have been deallocated [allocatable]).
Regarding claim 11, Desai teaches a device (Paragraph 21; Fig. 1, SSD 101) comprising:
at least one circuit (Paragraph 21; Fig. 1, controller 103 [circuit] including flash translation layer 108 and front-end module 106);
memory media; and storage media (Paragraph 21; Fig. 1, SSD 101 including non-volatile memory 114 and volatile memory 121 [collectively memory and storage media]);
wherein the at least one circuit is configured to perform one or more operations comprising: receiving, using a memory access protocol, a request to make a region of memory on at least one of the memory media and the storage media allocatable (Paragraphs 22-24; Fig. 1, flash translation layer 108 of controller 103 [circuit] receives a deallocate command including specified address ranges within SSD 101 [memory/storage media] in NVMExpress protocol),
the request comprising a memory address range and an operation indicator indicating the request to make the region of memory allocatable (Paragraphs 17, 22, the deallocate command includes an LBA range (the command also includes an indication that it is a deallocate command to distinguish it from other commands));
determining that the at least one circuit has received the request to make the region of memory on at least one of the memory media and the storage media allocatable (Paragraphs 22, 24-25; Fig. 1, sending a response to front end module 106 via flash translation layer 108 [circuit] following receiving the deallocate command targeting LBA ranges in SSD 101 at flash translation layer 108);
and making the region of memory on at least one of the memory media and storage media allocatable based on determining that the at least one circuit has received the request (Paragraphs 22, 25; Fig. 1, in response to the deallocate command being received by front end module 106 via flash translation layer 108 [circuit], controller 103 deallocates [makes allocatable] the targeted LBA ranges in SSD 101).
Desai does not explicitly teach a device configured as expansion memory and performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from making the region of memory on at least one of the memory media and storage media allocatable.
However, Liu teaches a device configured as expansion memory (Paragraph 16; Fig. 1, multiple connectable storage systems 191, 192).
Desai and Liu are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Desai to further include the expansion memory according to the teachings of Liu. The motivation for doing so would have been to increase memory capacity.
Desai in view of Liu does not explicitly teach performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from making the region of memory on at least one of the memory media and storage media allocatable.
However, Ben Dayan teaches performing a garbage collection operation as a background process (Paragraph 49, SSDs may run a background garbage collection process),
wherein the garbage collection operation is performed as a separate operation from making the region of memory on at least one of the memory media and storage media allocatable (Paragraphs 49, 51-52, SSDs may run the garbage collection in the background following the processing of a trim/deallocate command [making allocatable]).
Desai, Liu, and Ben Dayan are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Desai in view of Liu to further include the background garbage collection process according to the teachings of Ben Dayan. The motivation for doing so would have been to ensure consistently low latency times (Ben Dayan, Paragraph 50).
Regarding claim 12, Desai in view of Liu, further in view of Ben Dayan teaches the device of claim 11, wherein the at least one circuit is further configured to perform one or more operations comprising: tracking addresses of allocated regions of memory on the device (Desai, Paragraph 25; Fig. 1, flash translation layer 108 uses L2P mapping table 122 to map [track] written addresses);
and modifying the at least one circuit to make available at least one address corresponding to the region of memory (Desai, Paragraph 25; Fig. 1, flash translation layer 108 is used to deallocate specified address ranges via L2P mapping table 122).
Regarding claim 13, Desai in view of Liu, further in view of Ben Dayan teaches the device of claim 11, wherein the device comprises a storage device, the storage device comprises the storage media (Desai, Paragraph 21; SSD 101 [storage device/media]), and the at least one circuit is further configured to perform one or more operations comprising:
sending, to the storage media, a command to make the region of memory allocatable (Desai, Paragraph 25; Fig. 1, flash translation layer 108 [circuit] sends a deallocate request including the specified address ranges to address translation hardware accelerator 120 of SSD 101 [storage media]);
wherein the storage media is configured to make the region of memory allocatable based on the command (Desai, Paragraph 25; Fig. 1, address translation hardware accelerator 120 of SSD 101 updates L2P mapping table 122 to deallocate address ranges specified in the command).
Regarding claim 14, Desai in view of Liu, further in view of Ben Dayan teaches the device of claim 11, wherein the storage media is further configured to perform one or more operations comprising: receiving, from the at least one circuit, a command to make allocatable the region of memory on the storage media (Desai, Paragraph 25; Fig. 1, address translation hardware accelerator 120 of SSD 101 [storage media] receives a deallocate command including the specified address ranges from flash translation layer 108 [circuit]).
Regarding claim 15, Desai in view of Liu, further in view of Ben Dayan teaches the device of claim 11, wherein the memory media is configured to perform one or more operations comprising: making allocatable the region of memory on the memory media (Desai, Paragraph 25; Fig. 1, SSD 101 [memory media] updates L2P mapping table 122 to deallocate the specified logical/physical address ranges).
Regarding claim 16, Desai in view of Liu, further in view of Ben Dayan teaches the device of claim 11, wherein the at least one circuit is further configured to perform one or more operations comprising: sending an indication that the region of memory is allocatable on the device (Desai, Paragraph 25; Fig. 1, front end module 106 [circuit] sends a deallocate completion status, indicating that the specified address ranges have been deallocated).
Regarding claim 17, Desai teaches a system comprising: a host device (Paragraph 21; Fig. 1, SSD system 100 includes a host 102) comprising:
at least one circuit (Paragraph 21; Fig. 1, controller 103 [circuit] includes flash translation layer 108);
memory media; and storage media (Paragraph 21; Fig. 1, SSD 101 including non-volatile memory 114 and volatile memory 121 [collectively memory and storage media]);
wherein the storage media comprises persistent storage (Paragraphs 21, 28; Fig. 1, SSD 101 comprises non-volatile memory 114 which retains data in the event of a power loss);
and the at least one circuit is configured to perform one or more operations comprising: receiving, from the host device, using a memory access protocol, a request to make a portion of the storage media allocatable (Paragraphs 22-24; Fig. 1, flash translation layer 108 of controller 103 [circuit] receives a deallocate command including specified address ranges from host 102 in NVMExpress protocol),
the request comprising a memory address range and an operation indicator indicating the request to make the portion of the storage media allocatable (Paragraphs 17, 22, the deallocate command includes an LBA range (the command also includes an indication that it is a deallocate command to distinguish it from other commands));
translating the portion of the storage media to one or more addresses (Paragraph 25; Fig. 1, flash translation layer 108 uses L2P mapping table 122 to translate logical and physical addresses);
determining that the at least one circuit has received the request to make the portion of storage media allocatable (Paragraph 24; Fig. 1, flash translation layer 108 of controller 103 receives the deallocate command and determines the offset);
making the portion of the storage media allocatable based on the determining (Paragraphs 24-25; Fig. 1, in response to the deallocate command, deallocating [making allocatable] the specified logical address ranges based on determining the offset, and updating the L2P mapping table 122 to indicate deallocated physical addresses [portion] of non-volatile memory 114 [storage media]);
and modifying the at least one circuit to make the one or more addresses available (Paragraph 25; Fig. 1, flash translation layer 108 is used to deallocate the specified address ranges via L2P mapping table 122).
Desai does not explicitly teach a memory device configured as expansion memory; and performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from the making the portion of storage media allocatable.
However, Liu teaches a memory device configured as expansion memory (Liu, Paragraph 16; Fig. 1, multiple connectable storage systems 191, 192).
Desai and Liu are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Desai to further include the expansion memory according to the teachings of Liu. The motivation for doing so would have been to increase memory capacity.
Desai in view of Liu does not explicitly teach performing a garbage collection operation as a background process, wherein the garbage collection operation is performed as a separate operation from the making the portion of storage media allocatable.
However, Ben Dayan teaches performing a garbage collection operation as a background process (Paragraph 49, SSDs may run a background garbage collection process),
wherein the garbage collection operation is performed as a separate operation from the making the portion of storage media allocatable (Paragraphs 49, 51-52, SSDs may run the garbage collection in the background following the processing of a trim/deallocate command).
Desai, Liu, and Ben Dayan are analogous art because they are in the same field of endeavor, that being data deallocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Desai in view of Liu to further include the background garbage collection process according to the teachings of Ben Dayan. The motivation for doing so would have been to ensure consistently low latency times (Ben Dayan, Paragraph 50).
Regarding claim 18, Desai in view of Liu, further in view of Ben Dayan teaches the system of claim 17, wherein the at least one circuit comprises a flash translation layer (Desai, Paragraph 21; Fig. 1, flash translation layer 108), and the at least one circuit is further configured to perform one or more operations comprising:
modifying the flash translation layer to make available addresses corresponding to the one or more addresses (Desai, Paragraph 25; Fig. 1, flash translation layer 108 is used to deallocate the specified logical/physical address ranges via L2P mapping table 122).
Regarding claim 19, Desai in view of Liu, further in view of Ben Dayan teaches the system of claim 17, wherein the at least one circuit is further configured to perform one or more operations comprising: sending a request to the storage media to make allocatable one or more regions of the storage media corresponding to the one or more addresses (Desai, Paragraph 25; Fig. 1, flash translation layer 108 sends a deallocate request including specified address ranges to address translation hardware accelerator 120 of SSD 101 [storage media]);
and the storage media is configured to perform one or more operations comprising: making allocatable the one or more regions of the storage media (Desai, Paragraph 25; Fig. 1, address translation hardware accelerator 120 of SSD 101 [storage media] updates L2P mapping table 122 to deallocate the specified address ranges).
Regarding claim 20, Desai in view of Liu, further in view of Ben Dayan teaches the system of claim 17, wherein making the portion of storage media allocatable comprises: marking one or more regions of the memory media allocatable corresponding to the one or more addresses (Desai, Paragraphs 22, 25; Fig. 1, controller 103 records [marks] targeted address ranges in SSD 101 with a “trim signature”, indicating that the addresses are deallocated [allocatable]).
Regarding claim 21, Desai in view of Liu, further in view of Ben Dayan teaches the method of claim 1, wherein making the region of memory allocatable is performed at a separate time from the garbage collection operation (Ben Dayan, Paragraphs 51-52, processing a trim/deallocate command prior to performing a garbage collection).
Response to Arguments
Applicant’s arguments (see pages 10-11 of the remarks) filed 6/8/2026, with respect to the rejections of claims 1-6 and 8-21 under 35 U.S.C 103 have been fully considered, but are not persuasive.
The Applicant argues that Desai, Ben Dayan, and particularly Liu fail to teach the amended limitation of claim 1 (and similarly claims 11 and 17): “making, using a second protocol, the region of memory allocatable based on determining that the circuit has received the request.” The Applicant states that the TRIM command of Liu fails to teach the limitation since TRIM commands are handled based on how the memory device implements TRIM commands. The Applicant also adds that Liu describes issuing the TRIM command to the storage array rather than making a region of memory allocatable.
However, although Liu teaches issuing a request to the storage array (Paragraph 25; Fig. 2, issuing a SATA TRIM command to a virtual solid-state memory device), Liu also teaches converting the request to a second protocol which makes a memory region allocatable in response (Paragraph 25; Fig. 2, translating the SATA TRIM command into an SCSI UNMAP command which further operates to delete blocks in a memory device). The Examiner notes that the TRIM command was used to teach the request while the UNMAP command was used to teach the making a region of memory allocatable.
Accordingly, the Examiner argues that the previously cited areas of the Liu reference teach the amended limitation and further notes any other arguments with respect to claims 1, 11, and 17 are consummate in scope with the argument above. Thus, the Examiner maintains the rejections set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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