Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 11.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 08/23/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/23/2024. The information disclosed therein was considered.
Specification
5. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “According to one embodiment” in page 1, line 1, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al (Pub. No.: US 2014/0334228 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Kim et al in Fiigures 1-8 are directly discloses a test apparatus (a system test apparatus 100, Figures 1A-1C) comprising:
an interface unit (a memory interface 122 and a host interface 121, Fig. 1B) that acquires a read characteristic (a memory read/write 106, Fig. 1A) indicating a relationship between a read voltage of a memory cell (a memory cell array 115, Fig. 1A) and a logarithm of a cell current, the memory cell (the memory cell array 115) being subject to write processing in which a write operation (a memory read/write 106, Fig. 1A) and a verification operation are repeated with increasing write voltage (the read/write circuitry 106 configured to generate signals that cause data to be written to or read from memory cells of the memory cell array 115 and the host interface 121/the memory interface 122 such as pass data that is to be stored in the memory device 110, Figures 1A-1B, column 2, paragraph 0028-0030); and
a controller (a memory controller 120, Figs. 1A-1B) that obtains a threshold voltage (a voltage VT ANALYZER 125, Fig. 1B) of the memory cell (the memory cell array 115, Fig. 1A) by performing first processing (a host 130, Fig. 1A) on the read characteristic (a memory read/write 106, Fig. 1A), the first processing (the host 130, Fig. 1A) being processing of, when a subthreshold region in the read characteristic is defined as a first region, focusing on a second region being a region of a read voltage larger than a maximum read voltage of the first region, calculates a first slope in a first threshold characteristic indicating a relationship between a write voltage (the read/write memory 106) and the threshold voltage (a voltage VT ANALYZER 125, Fig. 1B) in the write processing, based on the threshold voltage obtained in the first processing (the host 130, Fig. 1A), and subtracts the first slope from a slope in a predetermined threshold characteristic to obtain a first slope degradation component (the memory controller 120 includes the memory read/write 106 for sense the voltage of the memory cells in the memory array 115 and compares the sensed voltage to one or more threshold voltage VT and the voltage level represents the data stored in the memory cell array 115, see at least in Figures 1A-1C, column 2, paragraph 0028 to column 4, paragraph 0042 and the related disclosures).
Allowable Subject Matter
7. Claims 2-10, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 2 and 6, the prior art fails to tech or suggest the claimed limitations, namely, the controller obtains the threshold voltage of the memory cell by performing second processing on the read characteristic, the second processing being processing of focusing on the first region in the read characteristic, calculates a second slope in a second threshold characteristic indicating a relationship between a write voltage and a threshold voltage in the write processing, based on the threshold voltage obtained in the second processing, and subtracts the second slope from the first slope to obtain a second slope degradation component.
With respected to dependent claim 3, the prior art fails to tech or suggest the claimed limitations, namely, the controller, as the first processing, obtains a threshold voltage corresponding to a tangent that maximizes an inclination of a waveform of the read characteristic.
With respected to dependent claim 4, the prior art fails to tech or suggest the claimed limitations, namely, the interface unit acquires a first read characteristic and a second read characteristic of a memory cell, and the controller, as the first processing, uses a third read characteristic and a fourth read characteristic obtained by non-logarithmically-converting the cell current in each of the first read characteristic and the second read characteristic to parallel-translate a duplication of a waveform of the third read characteristic in a read voltage direction so as to fit the duplication of the waveform of the third read characteristic to a waveform of the fourth read characteristic, logarithmically-converts the cell current in the fitted third read characteristic to obtain a waveform of a fifth read characteristic, and uses the waveform of the fifth read characteristic to obtain a threshold voltage corresponding to the second read characteristic.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, the first slope degradation component indicates degradation related to carrier capture efficiency of the memory cell.
With respected to dependent claims 7-8 and 10, the prior art fails to tech or suggest the claimed limitations, namely, the interface unit acquires a read characteristic indicating a relationship between a read voltage of the memory cell and a logarithm of a cell current, the memory cell being subject to erase processing in which an erase operation and a verification operation are repeated with increasing erase voltage, and the controller performs the first processing on the read characteristic to obtain a threshold voltage of the memory cell, calculates a third slope in a third threshold characteristic indicating a relationship between an erase voltage and a threshold voltage in the erase processing, based on the threshold voltage obtained in the first processing, and subtracts the third slope from the slope in the predetermined threshold characteristic to obtain a third slope degradation component.
With respected to dependent claim 9, the prior art fails to tech or suggest the claimed limitations, namely, the predetermined threshold characteristic is a threshold characteristic obtained based on an ideal condition
8. Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 11: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “obtaining a threshold voltage of the memory cell by performing first processing on the read characteristic, the first processing being processing of, when a subthreshold region in the read characteristic is defined as a first region, focusing on a second region being a region of a read voltage larger than a maximum read voltage of the first region; calculating a first slope in a threshold characteristic indicating a relationship between a write voltage and the threshold voltage in the write processing, based on the threshold voltage obtained in the first processing; and subtracting the calculated first slope from a slope in a predetermined threshold characteristic to obtain a first slope degradation component” in a test method as claimed in the independent claim 11. Claims 12-20 are also allowed because of their dependency on claim 11.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kamano et al (US. 2006/0200714 A1) discloses test equipment for semiconductor.
Grobis et al (US. 11,894,037 B2) discloses first fire and cold start in memory with threshold switching selectors.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov