CTNF 18/814,701 CTNF 88139 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 2, 9, 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, 15 of U.S. Patent No. 12094029 and claims of 4, 6, 11, 13, 18, 20 of U.S. Patent No. 10319064. Although the claims at issue are not identical, they are not patentably distinct from each other. The table below helps illustrate the double patenting rejection: Claim 2 of App. No. 18814701 Claim 1 of U.S. Patent No. 12094029 A computing system comprising: a central processing unit; a graphics processing unit; and a memory coupled to one or more of the central processing unit or the graphics processing unit, the memory including a set of instructions, which when executed by the one or more of the central processing unit or the graphics processing unit, cause the computing system to: store a mask; apply the mask to a first shader pass, wherein the mask covers a pixel ; and apply an inverse of the mask to a second shader pass, wherein the inverse of the mask covers the pixel . A computing system comprising: a central processing unit; a graphics processing unit; and a memory coupled to one or more of the central processing unit or the graphics processing unit, the memory including a set of instructions, which when executed by the one or more of the central processing unit or the graphics processing unit, cause the computing system to: store a mask; apply the mask to a first shader pass to determine that one or more inside anti-aliasing sample locations of a first pixel are inside the mask and a determine that one or more outside anti-aliasing sample locations of the first pixel that are outside the mask are to be bypassed; and apply an inverse of the mask to a second shader pass. As clearly shown above, although the claims at issue are not identical, they are not patentably distinct from each other, as the only difference between claim 2 of the instance application and claim 1 of the U.S. Patent is wherein the mask covers a pixel. However, this is obvious in view of the U.S. Patent’s limitation of “determine that one or more inside anti-aliasing sample locations of a first pixel are inside the mask,” as a determination that a pixel is inside (covered) by the mask is made. Hence, the claims at issue are not patentably distinct from each other. The table below shows the mapping of the conflicting claims of the instance application and U.S. Patent No. 12094029: App. No. 18814701 U.S. Patent No. 12094029 2 1 9 8 16 15 The table below shows the mapping of the conflicting claims of the instance application and U.S. Patent No. 10319064: App. No. 18814701 U.S. Patent No. 10319064 2 4 & 6 9 11 & 13 16 18 & 20 Allowable Subject Matter Claims 2, 9, 16 are rejected under double patenting, but would be allowable in view of a properly filed terminal disclaimer. Furthermore, the dependent claims are objected to as being dependent upon a rejected base claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Peter Hoang whose telephone number is (571)270-1346. The examiner can normally be reached Monday-Friday 8:00 am - 5:00 pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hajnik F. Daniel can be reached at (571) 272-7642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER HOANG/ Primary Examiner, Art Unit 2616 Application/Control Number: 18/814,701 Page 2 Art Unit: 2616 Application/Control Number: 18/814,701 Page 3 Art Unit: 2616 Application/Control Number: 18/814,701 Page 4 Art Unit: 2616
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