Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 8, 9, 11 and 15 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Cho et al. (hereinafter Cho) (US 20200210079 A1).
As to claim 1, Cho teaches a storage device [FIG. 1: SSD 1] comprising:
a memory device [volatile memory 20];
at least one non-volatile memory device [non-volatile memory 30];
a controller [FIG. 1: controller 10] configured to control the memory device and the at least one non-volatile memory device [0024: “The controller 10 may control the overall operation of the SSD 1. For example, the controller 10 may control the volatile memory 20 and the non-volatile memory 30 to read or program data in response to a request of a host.”]; and
a power management chip [FIG. 1: PMIC 40] configured to supply power voltages corresponding to the memory device, the at least one non-volatile memory device, and the controller [0027: “The power management integrated circuit 40 may control power supplied to components of the SSD 1 to drive the SSD 1.”],
wherein the power management chip includes a multi-time programmable (MTP) memory storing the hardware set data [FIG. 2: active register and standby register] [0029 : “a power management integrated circuit 40 may include an active register 41, a standby register 43”] [0030: “The active register 41 and the standby register 43 may store a plurality of control data used to control an operation of the power management integrated circuit 40.”]
wherein the storage device is configured to have an initialization operation performed therefor using a hardware set data, after performing a power-on operation of the storage device [0030 : “For example, the active register 41 may be configured to store active mode control data used for switching an SSD from a low power mode to an active mode,”] [0031: “The power management integrated circuit 40 may generate a power control signal for controlling power of each of the components of the SSD by using the active mode control data stored in the active register 41.”].
As to claim 3, Cho teaches wherein the storage device is configured to have a low power mode setting operation performed therefor using the hardware set data in response to a low power mode request from an external device [0030: “the standby register 43 may be configured to store low power mode control data used for switching the SSD from the active mode to the low power mode.”] [0058: “the PMIC may receive a select signal from a source external to the SSD (e.g., from at least one processor of the computer) so that this mode switching may be reflected in a SSD state.”].
As to claim 4, Cho teaches wherein the storage device is configured to have at least one of a target voltage, an undervoltage lockout (UVLO) level, or a power on/off scenario changed using the hardware set data [0048: “The active mode control data and the low power mode control data each may include at least one among enable control data, discharge control data, pulse control data, and/or voltage level control data. In particular, the low power mode control data may further include delay control data.”] [0049-0053].
As to claim 5, Cho teaches wherein the hardware set data comprises a target voltage, an undervoltage lockout (UVLO) voltage, a power off delay time, a low power mode scenario, a forced discharge value, a pulse width modulation (PWM)/forced PWM (fPWM) mode, or a soft turn off resistor (RSTO) delay time [0048: “The active mode control data and the low power mode control data each may include at least one among enable control data, discharge control data, pulse control data, and/or voltage level control data. In particular, the low power mode control data may further include delay control data.”] [0049-0053].
As to claim 8, Cho teaches wherein the power management chip is configured to enter or exit a low power mode in response to a power control signal without a command according to inter-integrated circuit (I2C) communication [0059: “the select signal may be input to one select signal receiving pin. Referring to FIG. 6, depicting operation S300 in detail according to some example embodiments, when a select signal is input to the one select signal receiving pin (S310), a signal (e.g., one or more power control signals) may be output in accordance with the active mode control data, or in accordance with low power mode control data, depending on whether the select signal is an rising edge or a falling edge.”].
As to claim 9, Cho teaches wherein the power management chip is configured to enter power gating in response to falling of the power control signal [0061: “If the select signal is a falling edge switching from High to Low (e.g., logic High to logic Low) (Yes in S340), the PMIC may output the signal (e.g., one or more power control signals) in accordance with the low power mode control data set and/or stored in S200) for use in switching from the active mode to the low power mode (S350).”], and wherein the power management chip is configured to exit power gating in response to rising of the power control signal [0060: “when the select signal is a rising edge switching from Low to High (e.g., logic Low to logic High) (Yes in S320), the PMIC may output the signal (e.g., one or more power control signals) in accordance with the active mode control data set and/or stored in S200) for use in switching from the low power mode to the active mode (S330).”].
As to claim 11, Cho teaches a method of operating a storage device, the method comprising:
performing a power-on operation of the storage device [0030 : “For example, the active register 41 may be configured to store active mode control data used for switching an SSD from a low power mode to an active mode…In an embodiment, the active mode control data and the low power mode control data may include data for supplying or cutting power to each of the components of the SSD, and data for controlling a level of the power supplied to each of the components of the SSD.”];
entering power gating in response to falling of a power control signal [0061: “If the select signal is a falling edge switching from High to Low (e.g., logic High to logic Low) (Yes in S340), the PMIC may output the signal (e.g., one or more power control signals) in accordance with the low power mode control data set and/or stored in S200) for use in switching from the active mode to the low power mode (S350).”];
exiting power gating in response to rising of the power control signal [0060: “when the select signal is a rising edge switching from Low to High (e.g., logic Low to logic High) (Yes in S320), the PMIC may output the signal (e.g., one or more power control signals) in accordance with the active mode control data set and/or stored in S200) for use in switching from the low power mode to the active mode (S330).”]; and
performing a power-off operation after the exiting power gating [0050: “To prepare for the event in which a control signal to exit the low power mode is generated within a short period (for example, within about 5 ms) following switching from the active mode to the low power mode, the PMIC according to some example embodiments may be prepared (e.g., configured) to address such errors by operating discharge circuits of a non-volatile memory. To this end, PMIC chips, SSDs, and SSD power-mode control methods according to some example embodiments may allow the power-off sequence control to progress smoothly by setting discharge control data contained in the active mode control data and/or the low power mode control data.”],
wherein a hardware setting is performed using set data stored in a multi-time programmable (MTP) memory of a power management chip of the storage device [0029 : “a power management integrated circuit 40 may include an active register 41, a standby register 43”], after the performing the power-on operation [0030 : “For example, the active register 41 may be configured to store active mode control data used for switching an SSD from a low power mode to an active mode,”] [0031: “The power management integrated circuit 40 may generate a power control signal for controlling power of each of the components of the SSD by using the active mode control data stored in the active register 41.”].
As to claim 15, Cho teaches the method of claim 11, further comprising receiving a low power mode request from an external device [0058: “the PMIC may receive a select signal from a source external to the SSD (e.g., from at least one processor of the computer) so that this mode switching may be reflected in a SSD state.”]; and reading set data from the MTP memory in response to the low power mode request; and setting the power management chip according to the set data [0030: “the standby register 43 may be configured to store low power mode control data used for switching the SSD from the active mode to the low power mode.”].
Claim(s) 16-19 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Yun et al. (hereinafter Yun) (US 20200333818 A1).
As to claim 16, Yun teaches a method of testing a plurality of storage devices [FIG. 11: memory device 2120] on a test board [FIG. 11: test equipment 2200], the method comprising:
performing a power-on operation of the plurality of storage devices [0086: “In operation S215, the test equipment 2200 may supply the power supply voltages VIN1, VIN2, and GND to the PMIC 2110. In operation S220, the PMIC 2110 may supply the power supply voltages VDD, VDDQ, and VPP to the memory device 2120.”];
applying a power voltage to a multi-time programmable (MTP) write-only pin of the test board [0086: the test equipment is supplying power to memory module. It means that there is power voltage being supplied to voltage output terminal of the test equipment.];
when applying the power voltage, transmitting hardware set data to each of the plurality of storage devices through inter-integrated circuit (I2C) communication [0087: “In operation S225, the test equipment 2200 may transmit the setting information received in operation S205 and the monitoring start command to the PMIC 2110 by using the SCL signal and the SDA signal.”] [0030: “The host 10 is a master device that may communicate with the PMIC 100. For example, the host 10 may drive a serial clock line SCL and a serial data line SDA between the host 10 and the PMIC 100 in compliance with a given communication protocol, such as a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I2C) protocol, or an I3C protocol.”]; and
after performing a test operation of each of the plurality of storage devices, performing a power-off operation of the plurality of storage devices [0076: “The test equipment 1200 may supply the power supply voltages VIN1, VIN2, and GND to the memory module 1100.”] [The test equipment supplies voltage to memory module for testing operation. After testing, the memory module is powered off once the voltage of VIN is stopped.],
wherein the hardware set data is stored in an MTP memory of a power management chip of each of the plurality of storage devices [0052: “ In operation S110, the interface circuit 120 may receive setting information from the host 10. The setting register 142 may store the setting information.”].
As to claim 17, Yun teaches wherein, when a ground voltage is applied to the MTP write-only pin, a write operation on the MTP memory is prohibited [0086: “In operation S215, the test equipment 2200 may supply the power supply voltages VIN1, VIN2, and GND to the PMIC 2110. In operation S220, the PMIC 2110 may supply the power supply voltages VDD, VDDQ, and VPP to the memory device 2120.”] [If no voltage is supplied to PMIC, no write operation is allowed.].
As to claim 18, Yun teaches wherein the test board comprises a printed circuit board (PCB) having the plurality of storage devices serially arranged thereon [FIG. 14: a test board is a host which comprises a PCB and storage device in general.].
As to claim 19, Yun teaches wherein, after the test operation, an individual storage device among the plurality of storage devices is cut from the PCB [power for storage device is cut after testing.].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (hereinafter Cho) (US 20200210079 A1) in view of Dropps (US 9698803 B1).
As to claims 2, Cho does not teach wherein the MTP memory is configured to store the hardware set data during a test operation in a manufacturing stage of the storage device.
Dropps teaches storing hardware set data during a test operation in a manufacturing stage [col. 7, lines 61-66: “In another aspect, the configuration data is stored in nonvolatile memory such as ROM, EPROM, EEPROM, Flash, phase change, disk, tape or other memory types. In yet another aspect, the configuration data is stored in fuses that are programmed during manufacturing test process.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of storing data during manufacturing test process as suggested in Dropps into Cho to implement data storing. One having ordinary skill in the art would have been motivated to make such modification to ensure product quality.
Claim(s) 6, 7, 12, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (hereinafter Cho) (US 20200210079 A1) in view of Yun et al. (hereinafter Yun) (US 20200333818 A1).
As to claim 6, Cho does not teach wherein the power management chip comprises an MTP write-only pin, a clock pin, and a data pin.
Yun teaches wherein the power management chip comprises an MTP write-only pin [FIG. 10: VIN 1/VIN2], a clock pin [FIG. 10: SCL], and a data pin [FIG. 10: SDA].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of designated communication pins in PMIC as suggested in Yun into Cho to implement communication between PMIC and host. One having ordinary skill in the art would have been motivated to make such modification to enhance security and communication speed.
As to claim 7, Yun further teaches wherein the clock pin and the data pin are configured to transfer and receive a clock and data, respectively, corresponding to an inter-integrated circuit (I2C) interface [0030: “The host 10 is a master device that may communicate with the PMIC 100. For example, the host 10 may drive a serial clock line SCL and a serial data line SDA between the host 10 and the PMIC 100 in compliance with a given communication protocol, such as a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I2C) protocol, or an I3C protocol. The host 10 may transmit an SCL signal (clock signal) to the PMIC 100 through the SCL and may transmit an SDA signal (data signal) synchronized with the SCL signal to the PMIC 100 through the SDA.”].
As to claim 12, Yun teaches the method of claim 11, further comprising writing the set data to the MTP memory in a testing stage of the storage device [0086: “the test equipment 2200 may generate a test pattern for testing the memory module 2100.”] [0087: “the test equipment 2200 may transmit the setting information received in operation S205 and the monitoring start command to the PMIC 2110 by using the SCL signal and the SDA signal.”].
As to claim 13, Yun teaches wherein the writing the set data to the MTP memory comprises transmitting the set data to the storage device connected to a test board through inter-integrated circuit (I2C) communication [0030: “The host 10 is a master device that may communicate with the PMIC 100. For example, the host 10 may drive a serial clock line SCL and a serial data line SDA between the host 10 and the PMIC 100 in compliance with a given communication protocol, such as a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I2C) protocol, or an I3C protocol. The host 10 may transmit an SCL signal (clock signal) to the PMIC 100 through the SCL and may transmit an SDA signal (data signal) synchronized with the SCL signal to the PMIC 100 through the SDA.”].
As to claim 14, Yu teaches wherein the test board comprises an MTP write-only terminal [FIG. 11: terminals for supply power to VIN1 and VIN 2 of PMIC], and wherein a write operation of the MTP memory is allowed or prohibited, depending on a voltage applied to the MTP write-only terminal [0086: “ In operation S215, the test equipment 2200 may supply the power supply voltages VIN1, VIN2, and GND to the PMIC 2110.”] [In order to write data into PMIC, an operating power has to be supplied to the PMIC first. No operating power, no write operation is allowed.].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (hereinafter Cho) (US 20200210079 A1) in view of Schulze et al. (hereinafter Schulze) (US 20170220080 A1).
As to claim 10, Cho does not teach wherein the storage device has a form factor having an M.2 specification.
Schulze teaches that a storage device has a form factor having an M.2 specification [0013: “the expansion card 106 can be a storage device that uses the M.2 specification as a connector to the PCB of the server 100.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of using M.2 specification as form factor for the storage device as suggested in Schulze into Cho to implement storage device’s form. One having ordinary skill in the art would have been motivated to make such modification to provide faster speed and more flexible connectivity.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (hereinafter Yun) (US 20200333818 A1) in view of Cho et al. (hereinafter Cho) (US 20200210079 A1).
As to claim 20, Yun does not teach wherein each of the plurality of storage devices rewrites the hardware set data stored in the MTP memory in response to a low power mode request.
Cho teaches wherein each of the plurality of storage devices rewrites the hardware set data stored in the MTP memory in response to a low power mode request [0030: “the standby register 43 may be configured to store low power mode control data used for switching the SSD from the active mode to the low power mode.”] [0058: “the PMIC may receive a select signal from a source external to the SSD (e.g., from at least one processor of the computer) so that this mode switching may be reflected in a SSD state.”] [a low power control data is written into PMIC for low power mode request.].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of writing setting data into memory for low power mode request as suggested in Cho into Yun to implement different mode testing. One having ordinary skill in the art would have been motivated to make such modification to improve the versatility of the system.
Conclusion
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/XUXING CHEN/ Primary Examiner, Art Unit 2176