DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, and their depending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6-8, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444).
In re claim 1, Fujita discloses a multilayer ceramic capacitor comprising:
a multilayer body (11 – Figure 5, ¶35);
and external electrodes (12a, 12b – Figure 4, Figure 5, ¶34);
the multilayer body including a multilayer chip including an inner layer portion (11e – Figure 5, ¶47) in which dielectric layers (13 – Figure 5, ¶45) and internal electrode layers (14 – Figure 5, ¶45) are alternately laminated on each other (Figure 5), and outer layer portions (11n below and above 14 – Figure 5, ¶49) respectively provided on both sides of the inner layer portion in a lamination direction (‘T’ direction – Figure 4, Figure 5), and side gap portions (11n adjacent to 115, 116 – Figure 6, ¶49) respectively provided on both sides of the multilayer chip in a width direction (‘W’ direction – Figure 5) that intersects with the lamination direction (‘T’ direction – Figure 5);
the external electrodes (12a, 12b – Figure 5) being respectively provided ends of the multilayer body (11 – Figure 5) in a length direction (‘L’ direction – Figure 5) that intersects with the lamination direction and the width direction (Figure 5, Figure 6);
wherein each of the dielectric layers includes Ba and Ti (¶50), and each of the internal electrode layers includes Ni (¶80);
a dimension of the multilayer body in the length direction is defined as a dimension L0 (L11 – Figure 5, ¶43), a dimension of the multilayer body in the lamination direction is defined as a dimension T0 (T11 – Figure 5, ¶43), a dimension of the multilayer body in the width direction is defined as a dimension W0 (W11 – Figure 5, ¶43), and 1.7 ≤ L0/T0 ≤ 2.3 (Table 1: First Working Example) and 1.0 ≤ W0/T0 ≤ 1.4 (Table 1: First Working Example) are satisfied;
a dimension of each of the side gap portions in the width direction is defined as a dimension WS (Wa, Wb – Figure 6, ¶13), a dimension of each of the outer layer portions in the lamination direction is defined as a dimension TG (Tb, Ta – Figure 6, ¶49), and 0.3 ≤ WS/TG ≤ 0.6 is satisfied (Table 1: First Working Example); and for each of the internal electrode layers, a dimension in the width direction is defined as a dimension WI (W11e – Figure 6, ¶47), and T0 < WI is satisfied (Table 1: First Working Example).
Fujita does not disclose in a cross section taken at a center in the length direction and extending in the lamination direction and the width direction, ends in the width direction of the internal electrode layers that are adjacent to each other in the lamination direction have a positional deviation d in the width direction, and the positional deviation d is about 5 μm or less.
Kitahara discloses taken at a center in the length direction and extending in the lamination direction and the width direction, ends in the width direction of the internal electrode layers that are adjacent to each other in the lamination direction have a positional deviation d in the width direction, and the positional deviation d is about 5 μm or less (¶41).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to reduce the positional deviation as described by Kitahara to provide for an electronic component having maximum capacitance.
Fujita does not disclose wherein a dimension of each of the dielectric layers in the lamination direction is defined as a dimension TD, and the dimension TD is about 0.67 μm or greater and about 0.73 μm or less. However, it is well-known in the art that adjusting the thickness of the dielectric layers is correlated to the capacitance of the device. It would have been an obvious matter of design choice to adjust the thickness of the dielectric layers to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Fujita does not disclose the dielectric layers each include a plurality of grains, and an average value GN of numbers of the grains arranged in the lamination direction in the dielectric layers is 3 or more and 4 or less.
Kim discloses that adjusting the grain size of a dielectric grain (11 – Figure 4, ¶30) is a balance between a change in dielectric constant and DC-bias properties (¶30). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the grain size, and thus number of grains arranged in the lamination direction, to achieve a device having desired capacitance and DC-bias properties, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Fujita does not disclose the internal electrode layers include interface-neighboring regions that are at interfaces between the internal electrode layers and the dielectric layers adjacent to the internal electrodes, and the interface-neighboring regions include Sn in a larger amount than other.
Cha discloses the internal electrode layers (121, 122 – Figure 3, Figure 4) include interface-neighboring regions (121a – Figure 4, ¶28) that are at interfaces between the internal electrode layers and the dielectric layers (111 – Figure 4, ¶28) adjacent to the internal electrodes (Figure 4), and the interface-neighboring regions include Sn in a larger amount than other portions of the internal electrode layers (121b – Figure 4, ¶28).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the composite layers of Cha to provide for an internal electrode that has small thickness deviation and improved connectivity (¶49: Cha).
In re claim 3, Fujita discloses a multilayer ceramic capacitor comprising:
a multilayer body (11 – Figure 5, ¶35);
and external electrodes (12a, 12b – Figure 4, Figure 5, ¶34);
the multilayer body including a multilayer chip including an inner layer portion (11e – Figure 5, ¶47) in which dielectric layers (13 – Figure 5, ¶45) and internal electrode layers (14 – Figure 5, ¶45) are alternately laminated on each other (Figure 5), and outer layer portions (11n below and above 14 – Figure 5, ¶49) respectively provided on both sides of the inner layer portion in a lamination direction (‘T’ direction – Figure 4, Figure 5), and side gap portions (11n adjacent to 115, 116 – Figure 6, ¶49) respectively provided on both sides of the multilayer chip in a width direction (‘W’ direction – Figure 5) that intersects with the lamination direction (‘T’ direction – Figure 5);
the external electrodes (12a, 12b – Figure 5) being respectively provided ends of the multilayer body (11 – Figure 5) in a length direction (‘L’ direction – Figure 5) that intersects with the lamination direction and the width direction (Figure 5, Figure 6);
wherein each of the dielectric layers includes Ba and Ti (¶50), and each of the internal electrode layers includes Ni (¶80);
a dimension of the multilayer body in the length direction is defined as a dimension L0 (L11 – Figure 5, ¶43), a dimension of the multilayer body in the lamination direction is defined as a dimension T0 (T11 – Figure 5, ¶43), a dimension of the multilayer body in the width direction is defined as a dimension W0 (W11 – Figure 5, ¶43), and 1.7 ≤ L0/T0 ≤ 2.3 (Table 1: First Working Example) and 1.0 ≤ W0/T0 ≤ 1.4 (Table 1: First Working Example) are satisfied;
a dimension of each of the side gap portions in the width direction is defined as a dimension WS (Wa, Wb – Figure 6, ¶13), a dimension of each of the outer layer portions in the lamination direction is defined as a dimension TG (Tb, Ta – Figure 6, ¶49), and 0.3 ≤ WS/TG ≤ 0.6 is satisfied (Table 1: First Working Example); and for each of the internal electrode layers, a dimension in the width direction is defined as a dimension WI (W11e – Figure 6, ¶47), and T0 < WI is satisfied (Table 1: First Working Example).
Fujita does not disclose in a cross section taken at a center in the length direction and extending in the lamination direction and the width direction, ends in the width direction of the internal electrode layers that are adjacent to each other in the lamination direction have a positional deviation d in the width direction, and the positional deviation d is about 5 μm or less.
Kitahara discloses taken at a center in the length direction and extending in the lamination direction and the width direction, ends in the width direction of the internal electrode layers that are adjacent to each other in the lamination direction have a positional deviation d in the width direction, and the positional deviation d is about 5 μm or less (¶41).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to reduce the positional deviation as described by Kitahara to provide for an electronic component having maximum capacitance.
Fujita does not disclose wherein a dimension of each of the dielectric layers in the lamination direction is defined as a dimension TD, and the dimension TD is about 0.85 μm or greater and about 0.91 μm or less. However, it is well-known in the art that adjusting the thickness of the dielectric layers is correlated to the capacitance of the device. It would have been an obvious matter of design choice to adjust the thickness of the dielectric layers to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Fujita does not disclose the dielectric layers each include a plurality of grains, and an average value GN of numbers of the grains arranged in the lamination direction in the dielectric layers is 3 or more and 4 or less.
Kim discloses that adjusting the grain size of a dielectric grain (11 – Figure 4, ¶30) is a balance between a change in dielectric constant and DC-bias properties (¶30). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the grain size, and thus number of grains arranged in the lamination direction, to achieve a device having desired capacitance and DC-bias properties, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Fujita does not disclose the internal electrode layers include interface-neighboring regions that are at interfaces between the internal electrode layers and the dielectric layers adjacent to the internal electrodes, and the interface-neighboring regions include Sn in a larger amount than other.
Cha discloses the internal electrode layers (121, 122 – Figure 3, Figure 4) include interface-neighboring regions (121a – Figure 4, ¶28) that are at interfaces between the internal electrode layers and the dielectric layers (111 – Figure 4, ¶28) adjacent to the internal electrodes (Figure 4), and the interface-neighboring regions include Sn in a larger amount than other portions of the internal electrode layers (121b – Figure 4, ¶28).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the composite layers of Cha to provide for an internal electrode that has small thickness deviation and improved connectivity (¶49: Cha).
In re claim 6, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita further discloses wherein the multilayer ceramic capacitor (10 – Figure 4, ¶31) has a substantially rectangular parallelepiped shape (Figure 4).
In re claim 7, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita further discloses wherein a ratio between L0 (L11 – Figure 5), T0 (T11 – Figure 5), and W0 (W11 – Figure 6) is about 2:1:1.2 (Table 1: First Working Example). Note that the dimension ratio disclosed in the First Working Example are considered to satisfy ‘about’ 2:1:1.2.
In re claim 8, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita further discloses wherein 0.4 ≤ WS/TG ≤ 0.5 is satisfied (Table 1: First Working Example discloses a side gap portion having a dimension of 18 µm and an outer layer portion having a thickness of 32 µm).
In re claim 9, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein the dimension TD is about 0.70 μm. However, it is well-known in the art that adjusting the thickness of the dielectric layers is correlated to the capacitance of the device. It would have been an obvious matter of design choice to adjust the thickness of the dielectric layers to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 10, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 9, as explained above. Fujita does not disclose wherein each of the grains has a grain diameter of about 150 nm or greater and about 200 nm or less.
Kim discloses that adjusting the grain size of a dielectric grain (11 – Figure 4, ¶30) is a balance between a change in dielectric constant and DC-bias properties (¶30). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the grain size to achieve a device having desired capacitance and DC-bias properties, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 11, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 9, as explained above. Fujita does not disclose wherein a number of the dielectric layers is 405 or more and 430 or less. However, it is well-known in the art that adjusting the number of dielectric layers, and thus, opposing internal electrode layers, is directly correlated to the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of dielectric layers to achieve a device of desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 12, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 3, as explained above. Fujita does not disclose wherein the dimension TD is about 0.88 μm. However, it is well-known in the art that adjusting the thickness of the dielectric layers is correlated to the capacitance of the device. It would have been an obvious matter of design choice to adjust the thickness of the dielectric layers to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 13, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 12, as explained above. Fujita does not disclose wherein each of the grains has a grain diameter of about 150 nm or greater and about 200 nm or less.
Kim discloses that adjusting the grain size of a dielectric grain (11 – Figure 4, ¶30) is a balance between a change in dielectric constant and DC-bias properties (¶30). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the grain size to achieve a device having desired capacitance and DC-bias properties, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 14, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 12, as explained above. Fujita does not disclose wherein a number of the dielectric layers is 350 or more and 375 or less. However, it is well-known in the art that adjusting the number of dielectric layers, and thus, opposing internal electrode layers, is directly correlated to the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of dielectric layers to achieve a device of desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 20, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein each of the internal electrode layers includes Ni and Sn.
Cha discloses wherein each of the internal electrode layers includes Ni and Sn (¶28).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the composite layers of Cha to provide for an internal electrode that has small thickness deviation and improved connectivity (¶49: Cha).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444) and in further view of Lee et al. (US Publication 2020/0411245).
In re claim 4, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita further discloses the dimension WS of each of the side gap portions in the width direction is about 15 μm or greater and about 20 μm or less (Table 1: First Working Example shows Ta and Tb having a thickness of 32 μm.).
Fujita does not disclose wherein the dimension L0 in the length direction is about 1.15 μm or greater and about 1.25 μm or less, the dimension W0 in the width direction is about 0.65 μm or greater and about 0.75 μm or less, and the dimension T0 in the lamination direction is about 0.55 μm or greater and about 0.65 μm or less.
However, it is well-known in the art that adjusting the size and number of internal electrode layers is correlated to the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the size and number of internal electrode layers, and thus the length, width, and thickness dimensions of the component body, to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Fujita does not disclose the dimension TG of each outer layer portion in the lamination direction is about 36 μm or greater and about 43 μm or less.
Lee discloses the thickness of the cover portions is a balance between miniaturization of the electronic component and moisture resistance (¶63-64). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the outer layer portions to achieve a device having desired miniaturization per user specifications and moisture resistance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444) and in further view of Mizuno et al. (US Publication 2022/0130608).
In re claim 5, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein the dielectric layers each include a plurality of grains;
each of the grains has a core-shell structure including a core and a shell surrounding the core; and
for each of the grains, a molar ratio of Ba in the core to Ti included in the grain is higher than a molar ratio of Ba in the shell to the Ti included in the grain.
Mizuno discloses wherein the dielectric layers each include a plurality of grains (2 – Figure 1) (¶29);
each of the grains has a core-shell structure including a core and a shell surrounding the core (¶29); and
for each of the grains, a molar ratio of Ba in the core to Ti included in the grain is higher than a molar ratio of Ba in the shell to the Ti included in the grain (¶29-31; Note that the rare earth element can be contained in the Ba-site, and therefore, the ratio of Ba contained in the shell to the total amount of Ti is lower than the ratio of Ba contained in the core to the total amount of Ti.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the dielectric grains as described by Mizuno to improve the temperature load life and reliability of the electronic component (¶27: Mizuno).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444) and in further view of Kim ‘013 (US Publication 2014/0301013).
In re claim 16, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein a grain diameter of each of the grains in the dielectric layers of the multilayer chip is larger than a grain diameter of each of the grains in the dielectric layers included in the side gap portions.
Kim ‘013 discloses wherein a grain diameter of each of the grains in the dielectric layers (Ga – Figure 3, ¶18) of the multilayer chip (110 – Figure 1, ¶39) is larger than a grain diameter of each of the grains in the dielectric layers included in the side gap portions (Gw – Figure 3, ¶17) (¶15).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the dielectric grain diameter of the capacitive and side gap portions to achieve a device having excellent reliability and moisture-resistance characteristics (¶136: Kim ‘013).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444) and in further view of Takashima et al. (US Publication 2010/0128413).
In re claim 17, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein a thickness of each of the internal electrode layers is about 0.49 μm or greater and about 0.55 μm or less.
Takashima discloses that adjusting the thickness of the internal electrodes is correlated to the ESR of the capacitive device (¶89, Abstract).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the internal electrodes to achieve a device having desired ESR characteristics, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US Publication 2018/0158608) in view of Kitahara et al. (US Publication 2022/0102077) and in further view of Kim et al. (US Publication 2021/0183572) and in further view of Cha et al. (US Publication 2020/0058444) and in further view of Hirai (US Publication 2023/0162916).
In re claim 18, Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein each of the internal electrode layers has voids where metal is missing.
Hirai discloses wherein each of the internal electrode layers (30 – Figure 2, Figure 4, ¶104) has voids (H – Figure 5, ¶104) where metal is missing (¶104).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the holes as described by Hirai to provide for a desired maximum electric field strength and improved reliability of the multilayer ceramic capacitor (¶106: Hirai).
In re claim 19, , Fujita in view of Kitahara and in further view of Kim and in further view of Cha discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fujita does not disclose wherein each of the internal electrode layers includes about 85% metal.
Hirai discloses wherein each of the internal electrode layers (30 – Figure 2, Figure 4) includes about 85% metal (¶104; Note the Examiner is taking 88% to be about 85%.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the holes and coverage as described by Hirai to provide for a desired maximum electric field strength and improved reliability of the multilayer ceramic capacitor (¶106: Hirai).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US Publication 2019/0304695) [¶62, ¶64], Figure 3
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/ARUN RAMASWAMY/Primary Examiner, Art Unit 2847
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