DETAILED ACTION
This action is responsive to the amendments filed on 2/17/2026.
Currently, claims 1, 29, and 36 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 29, and 36 have been considered but are moot because the new ground of rejection as necessitated by the Applicant’s filed amendments (on 2/17/2026).
To clarify, Applicant’s filed amendments changed the scope of the claims such that the amendment claims overcome(s) the previous rejections under 35 U.S.C. 102 (with respect to Peng et al. (US 2021/0265965) reference for originally claims 1 and 36 (as filed on 11/11/2024)), and 35 U.S.C. 103 (with respect to Peng et al. (US 2021/0265965) reference in view of Gebeyehu et al. (US 2018/0316311) reference, as filed on 11/11/2024) in regards to the FAOMs mailed on 9/15/2025.
Where the Examiner notes that Applicant’s originally filed claims, as of 11/11/2024, were originally directed to the embodiment(s) of instant figures 5+6. However, the instant amendments (filed on 2/17/2026) change/shift the scope of the instant claims from instant figs. 5+6 to instant figure 4
Additionally but not exclusively, the examiner notes the similarity of the instant claims (i.e. currently amended claims) as filed on 2/17/2026 to the claims of the Parent Patent (USPN 12,074,576). However, the instant claims (i.e. currently amended claims) as filed on 2/17/2026 are far broader than the claims of Parent Patent (USPN 12,074,576); and thus the instant/currently claims (as filed on 2/17/2026) still read(s) upon the known prior art of record, specifically Gebeyehu et al. (US 2018/0316311) reference. The specific mapping and rationale for the new/updated rejections under 35 U.S.C 102 for claims 1, 29, and 36 (regarding the Gebeyehu et al. (US 2018/0316311) reference) are stated below:
With regards to claim 1, Gebeyehu teaches a power amplifier (see figs. 1 and 3-6: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4) comprising (addressed below):
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent);
a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”); and
a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 29, Gebeyehu teaches a semiconductor die (see figs. 1 and 3-6 and 7a/b: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4. Where the semiconductor die is mapped shown by figures 7a and 7b, that include previously addressed PA system (e.g. at least figures 5a-c and 6), e.g. see at least [0127-0136]) comprising (addressed below):
a substrate (figs. 1 and 3-6 and 7a/b: see [0127-0136], where the semiconductor die includes a substrate further including (or at least attached to) the PA system [0127-0136]); and
a power amplifier implemented on the substrate (previously addressed and/or readily apparent), the power amplifier (previously addressed) including[:] (addressed below)
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent),
the power amplifier (previously addressed) further including a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”),
the power amplifier (previously addressed) further including a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 36, Gebeyehu teaches a wireless device (see figs. 1 and 3-6: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4) comprising:
a transceiver (figs. 1 and 3-6: the wireless transceiver device was previously addressed. Moreover, figures 1 and 3 explicitly state/show a transceiver 802/33. Where the previously addressed transceiver (e.g. 802/33) generates a signal (for transmission), see the output of the transceiver in the direction of the PA system and antenna (as shown in figs. 1 and 3)) configured to generate a signal (previously addressed and/or readily apparent);
a power amplifier (figs. 1 and 3-6: in regards to figs. 1+3, see the transceiver 802/33 which generates and outputs a ‘modulated’ signal to previously addressed PA system (e.g. see the PA system of figure 1 and/or figure 3)) configured to amplify the signal (previously addressed and/or readily apparent), the power amplifier (previously addressed) including[:] (addressed below)
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent),
the power amplifier (previously addressed) further including a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”),
the power amplifier (previously addressed) further including a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent); and
an antenna in communication with the power amplifier (figs. 1 and 3-6: where at least figs. 1 and 3 each show that after the previously addressed PA system follows at least one antenna used for wireless communication/transmission (e.g. via antenna(s) 804/22)) and configured to support transmission of the amplified signal provided by the power amplifier (figs. 1 and 3-6: where at least figs. 1 and 3 each show that after the previously addressed PA system follows (or outputs to) at least one antenna used for wireless/RF communication/transmission (e.g. via antenna(s) 804/22). Where the remaining limitations were previously addressed and/or are readily apparent).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 29, and 36 are concurrently rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gebeyehu et al. (US 2018/0316311: hereinafter “Gebeyehu”).
With regards to claim 1, Gebeyehu teaches a power amplifier (see figs. 1 and 3-6: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4) comprising (addressed below):
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent);
a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”); and
a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 29, Gebeyehu teaches a semiconductor die (see figs. 1 and 3-6 and 7a/b: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4. Where the semiconductor die is mapped shown by figures 7a and 7b, that include previously addressed PA system (e.g. at least figures 5a-c and 6), e.g. see at least [0127-0136]) comprising (addressed below):
a substrate (figs. 1 and 3-6 and 7a/b: see [0127-0136], where the semiconductor die includes a substrate further including (or at least attached to) the PA system [0127-0136]); and
a power amplifier implemented on the substrate (previously addressed and/or readily apparent), the power amplifier (previously addressed) including[:] (addressed below)
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent),
the power amplifier (previously addressed) further including a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”),
the power amplifier (previously addressed) further including a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 36, Gebeyehu teaches a wireless device (see figs. 1 and 3-6: where figures 5a-c and 6 show nested circuitry within a power amplifier (PA) system ([0028-0031]), implemented within the wireless transceiver device of earlier of fig. 1 and/or fig. 3 and/or fig. 4) comprising:
a transceiver (figs. 1 and 3-6: the wireless transceiver device was previously addressed. Moreover, figures 1 and 3 explicitly state/show a transceiver 802/33. Where the previously addressed transceiver (e.g. 802/33) generates a signal (for transmission), see the output of the transceiver in the direction of the PA system and antenna (as shown in figs. 1 and 3)) configured to generate a signal (previously addressed and/or readily apparent);
a power amplifier (figs. 1 and 3-6: in regards to figs. 1+3, see the transceiver 802/33 which generates and outputs a ‘modulated’ signal to previously addressed PA system (e.g. see the PA system of figure 1 and/or figure 3)) configured to amplify the signal (previously addressed and/or readily apparent), the power amplifier (previously addressed) including[:] (addressed below)
an input stage that includes an amplifying transistor having an input node and an output node (figs. 1 and 3-6: see figure 6 (in view of the context of figs. 5a-5c), where the input stage is mapped to at least the input amplifying transistor 211 of the PA system of figure 6. Also see [0089] which states “As shown in FIG. 5a, the power amplifier 70 receives an RF input signal RF_IN, which is amplified using the input stage bipolar transistor 81. A collector of the input stage bipolar transistor 81 generates an amplified RF signal, which is provided to a base of the output stage bipolar transistor 82” (emphasis added).
Again, the Examiner notes that figure 6 is a more detailed version of circuitry of figs. 5a-5c. Where input stage transistor 211 (of PA system 290) and input stage transistor 81; are both ‘amplifying transistors’.
Furthermore, the gate of transistor 211 (of figure 6) is connected to the ‘input node’ and the top/collector of transistor 211 (also connected to resistor 220) is connected to the ‘output node’), such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level (previously addressed and/or readily apparent),
the power amplifier (previously addressed) further including a feedback circuit that couples the output node to the input node (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”), the feedback circuit including a resistance and a capacitance arranged in series (figs. 1 and 3-6: see figure 6 [Wingdings font/0xE0] resistor 220 and capacitor 219 which are serially connected to each other, and are feedback circuits between the input and output nodes of transistor 211 (as shown graphically in figure 6). Also see [0119] [Wingdings font/0xE0] “a feedback capacitor 219, and a feedback resistor 220”),
the power amplifier (previously addressed) further including a gain compensation circuit (figs. 1 and 3-6: power management circuit 201 and controlled/selected operation for envelope tracking 208 (ET) mode or average power tracking (APT) mode (via the DC-to-DC converter 207), where power management circuit 201 is implemented along an output path from the output node (as shown by the output node of transistor 211 being electrically connected to power management circuit 201 and VCC1 (via inductors L1 and L3 of figure 6). Where VCC1 is the first supply voltage (generated by power management circuit 201) and is stated to control the ‘gain’ of first/input stage amplifier/transistor of the power amplifier system (as addressed by figure 3 and [0077]). Additionally, both ET and APT modes are each stated to ‘control the outputted power amplifier supply voltage’ which sets the specific value of VCC1 that further sets/controls the gain of input amplifier/transistor of the PA system (see [0112]). Also see [0068].
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6) implemented along an output path from the output node (previously addressed and/or readily apparent) and configured to adjust the second power level based on a variation in an operating condition associated with the power amplifier (figs. 1 and 3-6: as previously addressed ET=envelope tracking and APT=average power tracking, in that context the power management circuit 201 adjusts/change the ‘second power level’ (output by amplifying transistor 211) based on variations in the operating condition (i.e. variations in the signal envelope during ET mode or variations in the signal’s average power during APT mode) the power amplifier (system) (at least power amplifier system 290 of figure 6).
Additionally but not exclusively, the AM/AM and AM/PM bias network of circuit 116/206 (figs. 5b/6) are stated to provide “gain expansion” (via nested feedforward capacitor 281 [0126]) according to ET mode or APT mode, see [0126]. Where bias network circuit 116/206 are ‘implemented along an output path from the output node’ as graphically shown by figure 5b/6. Which also adjust the second power level based on a variation in an operating condition (e.g. detected AM/AM or AM/PM signal variations) associated with the power amplifier system 130/290.
The remaining limitations were previously addressed and/or are readily apparent); and
an antenna in communication with the power amplifier (figs. 1 and 3-6: where at least figs. 1 and 3 each show that after the previously addressed PA system follows at least one antenna used for wireless communication/transmission (e.g. via antenna(s) 804/22)) and configured to support transmission of the amplified signal provided by the power amplifier (figs. 1 and 3-6: where at least figs. 1 and 3 each show that after the previously addressed PA system follows (or outputs to) at least one antenna used for wireless/RF communication/transmission (e.g. via antenna(s) 804/22). Where the remaining limitations were previously addressed and/or are readily apparent).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and are cited in the attached PTO-892 form.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAMES M PEREZ/Primary Examiner, Art Unit 2635 5/28/2026
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