Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/16/2026 has been entered.
Response to Arguments
Applicants' arguments filed on 07/16/2026 with respect to independent claims 1 and 9 are persuasive. Accordingly, claims 1-16 are allowed. However, claims 17-20 are not amended in a manner corresponding to claim 1 and therefore remain subject to the rejection for the reasons set forth in the previous Office Action.
It is noted that if independent claim 17 were amended in a manner similar to claim 1 to overcome the above discussed issue, the application would be in condition for allowance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which thepatent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WATANABE (US Pub. 2024/0248644).
Regarding independent claim 17, WATANABE discloses a non-transitory computer storage medium storing instruction which, when executed in a memory sub-system (Fig.1: The information processing system 1), cause the memory sub-system to perform a method, comprising:
allocating, from a random access memory (Fig.1: RAM - volatile memory 22) of the memory sub-system (Fig.1: The information processing system 1), one or more buffers (Fig.1: data buffer 221);
associating the one or more buffers (Fig.1: data buffer 221) respectively with one or more submission queues (Fig.1: submission queue 0, 1, 2. i.e., SQ0, SQ1, SQ2) among a plurality of submission queues (Fig.1: submission queue 0, 1, 2. i.e., SQ0, SQ1, SQ2) configured for a host system to communicate commands to access a storage capacity of the memory sub-system (Fig.1: submission queue 0, 1, 2. i.e., SQ0, SQ1, SQ2) ([0034]: The RAM 22 is, for example, a volatile memory. The RAM 22 is also called a main memory, a system memory, or a host memory. The RAM 22 is, for example, a dynamic random access memory (DRAM). In a storage area of the RAM 22, a buffer area that is used as a data buffer 221, an area of one or more submission queues SQ, and an area of one or more completion queues CQ are allocated);
loading data into a first buffer among the one or more buffers (Fig.1: data buffer 221) ([0035]: The data buffer 221 is a storage area that temporarily stores user data to be written into the SSD 3 and user data read from the SSD 3.);
retrieving, from a first submission queue associated with the first buffer among the plurality of the submission queues (Fig.1: submission queue 0, 1, 2. i.e., SQ0, SQ1, SQ2) ([0057]-[0059]: [0057] The CPU 43 is, for example, at least one processor. The CPU 43 controls the host I/F 41, the SRAM 42, the DMAC 44, the NAND I/F 45, and the DRAM I/F 46. The CPU 43 loads a control program (firmware) stored in the NAND memory 5 or a ROM (not illustrated) to the DRAM 6. The CPU 43 executes various processes by executing the loaded firmware. The firmware may be loaded to the SRAM 42. And the DMAC 44 is a circuit that executes direct memory access. The DMAC 44 executes data transmission between the RAM 22 of the host 2 and the SRAM 42 or the DRAM 6. For example, the DMAC 44 transmits data stored in the read buffer 61 to the data buffer 221. The DMAC 44 transmits data stored in the data buffer 221 to the write buffer 62); and
a first command configured to access the storage capacity; and executing the first command using the data in the first buffer ([0075]: Step 5: The controller 4 executes each of the fetched commands. The order in which the commands are executed is not limited, and the commands may be executed in a different order from the order in which the commands were fetched. In the process of executing each of the commands, the controller 4 executes transmission of data from the data buffer 221 of the host 2 to the write buffer 62 of the controller 4 or transmission of data from the read buffer 61 to the data buffer 221 of the host 2 as needed.).
Regarding claim 18, WATANABE teaches wherein the first buffer is allocated specifically for association with the first submission queue among the plurality of submission queues ([0034]: The RAM 22 is, for example, a volatile memory. The RAM 22 is also called a main memory, a system memory, or a host memory. The RAM 22 is, for example, a dynamic random access memory (DRAM). In a storage area of the RAM 22, a buffer area that is used as a data buffer 221, an area of one or more submission queues SQ, and an area of one or more completion queues CQ are allocated).
Allowable Subject Matter
Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 19 identifies the distinct features “wherein the method further comprises: retrieving a second command from the first submission queue; determining a size of a data chunk addressed for access by the second command; and determining a size of the first buffer based on the size of the data chunk addressed by the second command retrieved from the first submission queue", which are not taught or suggested by the prior art of records.
Claim 20, which respectively depends on objected-to claim 19, is allowable for at least the same reasons as claim 19.
Claims 19 and 20 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Reasons of Allowance
Claims 1-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Independent Claims 1 and 9 identify the distinct features “at least one processing device configured to: allocate, from the random access memory, one or more buffers; associate the one or more buffers respectively with one or more submission queues among the plurality of submission queues; load data from the storage medium of the memory sub-system to a first buffer among the one or more buffers; retrieve, from a first submission queue associated with the first buffer among the plurality of the submission queues, a first command configured to access the storage medium; execute the first command using the data in the first buffer; retrieve a second command from the first submission queue; determine a size of a data chunk addressed for access by the second command; and determine a size of the first buffer based on the size of the data chunk addressed by the second command retrieved from the first submission queue.", which are not taught or suggested by the prior art of records.
Claims 1-16 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records. The above features in conjunction with all other limitations of the dependent and independent claims 1-16 are hereby allowed.
Conclusion
Any inquiry concerning this comm1unication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 9:30am to 6:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PMR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-irect.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/YONG J CHOE/Primary Examiner, Art Unit 2135
Prosecution Insights