DETAILED ACTION
The current Office Action is in response to the papers submitted 07/16/2026. Claims 1 – 2, 4 – 12, and 14 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 4, 6 – 9 , 11 – 12, 14, 16 – 17, and 19 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matturi et al. (Pub. No.: US 2022/0222012) referred to as Matturi in view of Microsoft (Computer Dictionary: Fifth Edition) referred to as Microsoft in view of Daoud et al. (Pub. No.: US 2022/0342601) referred to as Daoud.
Regarding claim 1, Matturi teaches a host disposed on a first board [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board];
a main memory device [106, Fig 1; 530, 555, and 590, Fig 5; Paragraph 0032; The controller 106 receives data and stores it for processing making it equivalent to the claimed main memory] and separate from the host [Paragraphs 0016 - 0017; The host is considered as only the chipset of 105. The chipset of the host is not part of the controller. The chipset is connected to the controller 106 showing they are separate from each other], the main memory device comprising a main memory [106, Fig 1; 530, 555, and 590, Fig 5; Paragraph 0032; The controller 106 receives data and stores it for processing making it equivalent to the claimed main memory] and a first memory processing unit [107, Fig 1; Item 107 is a device that processes data by compressing or decompressing the data].
an external memory device disposed on a second board [110, Fig 1; Paragraph 0014; A DIMM is a separate board that is connected to other boards of a system] different from the first board [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board], the external memory device comprising a non-volatile memory device [130-a, Fig 1] and a second memory processing unit [115, Fig 1],
wherein the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board] is configured to transmit a swap-in request for compressed data [550 and 585, Fig 5; Paragraphs 0032 and 0074 - 0075; The read command the host sends out is a swap-in request for compressed data]
the external memory device [110, Fig 1] is configured to transfer the compressed data to the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board] in response to the swap-in request from the host [585 and 590, Fig 5; Paragraphs 0074 – 0075; The read command from the host system swaps in compressed data when the read data was compressed and stored previously in the external memory 110]; and
wherein the first memory processing unit [107, Fig 1] comprises a logic circuit configured to receive the compressed data from the external memory device [110, Fig 1] via the host [105, Fig 1; Paragraphs 0016 - 0017; Item 107 is inside the host system 105 showing the host part of 105 receives the data from the external memory 131 and transfers it to item 107 for processing such as an interface to allow data communication], decompress the compressed data to obtain decompressed data, and store the decompressed data in the main memory of the main memory device [106, Fig 1; 505, Fig 5; Paragraphs 0032, 0041 and 0069; The compressed data is decompressed in the controller and read by the host. Reading shows the use of a main memory in the controller to store the decompressed data to be read by the host].
the second memory processing unit [115, Fig 1] comprises a logic circuit configured to receive data from the main memory [106, Fig 1; 530, 555, and 590, Fig 5; Paragraph 0032; The controller 106 receives data and stores it for processing making it equivalent to the claimed main memory] in response to a swap-out request [575, Fig 5], and compress the received data to obtain compressed data [535, Fig 5], and
the non-volatile memory device is configured to store the compressed data [130-a, Fig 1; 575, Fig 5].
However, Matturi may not specifically disclose the limitation(s) of a main memory device disposed on the first board and a second processing unit compressing received data to obtain compressed data in a memory device.
Microsoft discloses a main memory device disposed on the first board [board, Page 66; Multiple components such as memory and chips can be mounted on a single board].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Microsoft in Matturi, because circuitry on the same board allows for increased data speeds between the circuitry on the board based in part on the circuitry being closer together based on data path length compared to the circuitry being on multiple different boards and being further away.
However, Matturi in view of Microsoft may not specifically disclose the limitation(s) of a second processing unit compressing received data to obtain compressed data in a memory device.
Daoud discloses a second processing unit [218, Fig 2] compressing received data to obtain compressed data in a memory device [210, Fig 2; 710 and 712, Fig 7; In step 710 the storage device received uncompressed data, compresses the uncompressed data, and then stores the compressed data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Daoud in Matturi in view of Microsoft, because it allows the system to balance operations between the host and the storage device based on the workload of the host so not to overburden the host with all the compression and decompression operations [Paragraphs 0018 – 0022].
Regarding claim 2, Matturi teaches a buffer [106, Fig 1; Fig 5] comprising the logic circuit of the first memory processing unit [107, Fig 1; 640, Fig 6; The controller comprises 107 and stores data to be compressed or decompressed making it equivalent to the buffer and the controller performs all steps under 505 in figure 5] is configured to:
store the compressed data [530 and 590, Fig 5; The host receives and stores the compressed data] received from the external memory device [110, Fig 1; Paragraphs 0072 and 0075; The nonvolatile memory sends compressed data to the controller when the nonvolatile memory contains compressed data] in the main memory [106, Fig 1; 505, Fig 5; The storage in the controller that stores either compressed or decompressed data is considered main memory],
perform a decompression operation on the compressed data to obtain the decompressed data [560, Fig 5],
transfer the decompressed data to the host [Paragraph 0016; The controller 106 transfers the decompressed data outside of the controller allowing the host to access and use the decompressed data], and
remove the compressed data from the main memory after the compressed data is decompressed [575, Fig 5; Paragraph 0072; The eviction of the compressed data is deleting the compressed data from the main memory in the controller].
Regarding claim 4, Matturi teaches the external memory device [110, Fig 1] is further configured to:
store non-compressed data classified as cold data [Paragraph 0039; Data is assigned a score indicating if data is hot or cold. Un-compressed data stored in the non-volatile memory that has not been accessed would have a low score or a score of zero making the score less than a threshold value and considered cold] in the non-volatile memory device [130-a, Fig 1],
store the compressed data in the non-volatile memory device [575, Fig 5], and
remove the non-compressed data from the non-volatile memory device after the compressed data is stored in the non-volatile memory device [575, Fig 5; Paragraph 0072; Non-compressed data is deleted from the non-volatile memory after a compressed version of the non-compressed data is stored in the non-volatile memory].
Doud discloses a memory device compressing the non-compressed data to obtain the compressed data [210, Fig 2; 710 and 712, Fig 7; In step 710 the storage device received uncompressed data, compresses the uncompressed data, and then stores the compressed data].
Regarding claim 6, Matturi teaches the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board] is configured to load the decompressed data from the main memory [560, Fig 5; Paragraphs 0011, 0032, and 0041; Read of the decompressed data is loading the decompressed data from the main memory where the decompressed data is stored after decompression] and use the compressed data [540, and 575, Fig 5; The compressed data is used by the host is commands to send data to memory devices].
Regarding claim 7, Matturi teaches the first memory processing unit [107, Fig 1] is on a layer adjacent to a host processor of the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset. Everything in the 105 is on an adjacent layer defined by the border of 105].
Regarding claim 8, Matturi teaches the main memory device [106, Fig 1] having the first memory processing unit [107, Fig 1] and the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board], and
the external memory device is disposed on a different board than the host [110, Fig 1; Paragraph 0014; A DIMM is a separate board that is connected to other boards of a system].
Microsoft discloses a main memory device disposed on the same board as the host [board, Page 66; Multiple components such as memory and chips can be mounted on a single board].
Regarding claim 9, Matturi teaches the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board] comprises a host processor [Paragraph 0016; A processor chipset is a processor in the host] having a cache corresponding to the main memory and the first memory processing unit [Paragraph 0016; Any memory in the host is considered cache including the memory used for the storage of compressed and uncompressed data in controller 106].
Regarding claim 19, Matturi teaches a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor [Paragraphs 0033 and 0097; Instructions are stored on non-transitory storage medium and executed by a processor] to perform the method of claim 11 [See rejections of claim 11].
Regarding claim 20, Matturi teaches a memory area configured to store data [106, Fig 1; 530, 555, and 590, Fig 5; Paragraph 0032, 0041 and 0069; The controller 106 receives data and stores it for processing making it equivalent to the claimed main area. Reading shows the use of a memory in the controller to store the decompressed to be read by the host and it is part of the same board as the host since the decompression happens in the host] , a host disposed on a board [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board];
a first memory processing unit [107, Fig 1; Item 107 is a device that processes data by compressing or decompressing the data] separate from the host [Paragraphs 0016 - 0017; The host is considered as only the chipset of 105. The chipset of the host is not part of the controller. The chipset is connected to the controller 106 showing they are separate from each other], wherein the first memory processing unit [107, Fig 1] comprises a logic circuit configured to decompress compressed data to obtain decompressed data, store the decompressed data in the memory area [106, Fig 1; 505, Fig 5; Paragraphs 0032, 0041 and 0069; The compressed data is decompressed in the controller and read by the host. Reading shows the use of a main memory in the controller to store the decompressed data to be read by the host], and transfer data to another memory device [540 and 575, Fig 5]; and
an external memory device [110, Fig 1] comprising a non-volatile memory device [130-a, Fig 1] and a second memory processing unit [115, Fig 1] disposed on a different board than the host [Paragraph 0014; A DIMM is a separate board that is connected to other boards of a system], wherein the second memory processing unit comprises a logic circuit configured to receive data from the memory area [106, Fig 1; 530, 555, and 590, Fig 5; Paragraph 0032; The controller 106 receives data and stores it for processing making it equivalent to the claimed memory area] in response to a swap-out request [575, Fig 5], and compress the received data to obtain compressed data [535, Fig 5], and the non-volatile memory device is configured to store the compressed data [575, Fig 5], and wherein the external memory device [110, Fig 1] is configured to transfer the compressed data to the host in response to a swap-in request [585 and 590, Fig 5; Paragraphs 0074 – 0075; The read command from the host system swaps in compressed data when the read data was compressed and stored previously in the external memory 110] from the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board].
However, Matturi may not specifically disclose the limitation(s) of a memory area and memory processing unit disposed on a same board as a host disposed on a same board as a host and a second memory processing unit compressing received data to obtain compressed data in a memory device.
Microsoft discloses a memory area and memory processing unit disposed on a same board as a host [board, Page 66; Multiple components such as memory and chips can be mounted on a single board].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Microsoft in Matturi, because circuitry on the same board allows for increased data speeds between the circuitry on the board based in part on the circuitry being closer together based on data path length compared to the circuitry being on multiple different boards and being further away.
However, Matturi in view of Microsoft may not specifically disclose the limitation(s) of a second processing unit compressing received data to obtain compressed data in a memory device.
Daoud discloses a second processing unit [218, Fig 2] compressing received data to obtain compressed data in a memory device [210, Fig 2; 710 and 712, Fig 7; In step 710 the storage device received uncompressed data, compresses the uncompressed data, and then stores the compressed data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Daoud in Matturi in view of Microsoft, because it allows the system to balance operations between the host and the storage device based on the workload of the host so not to overburden the host with all the compression and decompression operations [Paragraphs 0018 – 0022].
Claims 11 – 12, 14, 16 – 17, and 19 are methods corresponding to claims 1 – 2, 4, 6 – 7, and 9 and are rejected using the same prior art and similar reasoning. Matturi in view of Microsoft in view of Daoud disclose methods performing the functions of the system [Matturi, Fig 5; Daoud, Fig 7].
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matturi et al. (Pub. No.: US 2022/0222012) referred to as Matturi in view of Microsoft (Computer Dictionary: Fifth Edition) referred to as Microsoft in view of Daoud et al. (Pub. No.: US 2022/0342601) referred to as Daoud as applied to claims 1 and 11 above, and further in view of Hand, III et al. (Pub. No: US 2006/0004957) referred to as Hand.
Regarding claim 5, Matturi teaches the external memory device [110, Fig 1] is further configured to receive data from the main memory [106, Fig 1] and store the data in the non-volatile memory device [130-a, Fig 1; 575, Fig 5; The non-volatile memory device receives and stores data from the main memory].
However, Matturi in view of Microsoft may not specifically disclose the limitations of the host is configured to classify data unused within a period as cold data, and a memory device is further configured to receive the data classified as cold data from a first memory and store the received data in a second memory.
Hand discloses the host [110 and 812, Fig 8(b); 905, Fig 9; 905, Fig 11; Items 110 and 812 which includes 905 are considered a host] is configured to classify data unused within a period as cold data, and a memory device is further configured to receive the data classified as cold data from a first memory and store the received data in a second memory [Fig 12(b); The data is determined to be hot or cold and based on the current location of the data the data is moved to a more appropriate storage medium if needed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Hand in Matturi in view of Microsoft in view of Daoud, because it allows data to be moved to different tiers of memory based on their access frequency thereby improving data access I/O by storing frequently accessed data on faster memory compared to storing less frequently accessed data in slower memory.
Claim 15 is a method corresponding to claim 5 and is rejected using the same prior art and similar reasoning. Matturi in view of Hand disclose methods performing the functions of the system [Matturi, Fig 5; Hand, Figs 12(a) – 12(e)].
Claim(s) 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matturi et al. (Pub. No.: US 2022/0222012) referred to as Matturi in view of Microsoft (Computer Dictionary: Fifth Edition) referred to as Microsoft in view of Daoud et al. (Pub. No.: US 2022/0342601) referred to as Daoud as applied to claims 9 and 11 above, and further in view of Paul Massiglia (THE RAID book: A STORAGE SYSTEM TECHNOLOGY HANDBOOK) referred to as Massiglia.
Regarding claim 10, Matturi teaches the host [Paragraph 0016; The host is considered as only the chipset of system 105 and a chipset is on a circuit board], an external memory device [110, Fig 1], additional external memory [131, Fig 1] disposed on a different board from the host [Paragraph 0031; The use of an interface to connect 131 to 105 shows memory 131 is on a separate board requiring an interface], compression of data [535, Fig 5], and decompression of data [560, Fig 5], and transferring data to multiple memory devices [540 and 575, Fig 5].
Daoud discloses any external memory device is configured to perform compression [210, Fig 2; 710 and 712, Fig 7; In step 710 the storage device received uncompressed data, compresses the uncompressed data, and then stores the compressed data].
However, Matturi in view of Microsoft may not specifically disclose the limitation(s) of the host is configured to: transfer data to the external memory device when a swap memory pool of the external memory device is available, and transfer data to the additional external memory device when the swap memory pool of the external memory device is unavailable.
However, Matturi in view of Microsoft in view of Daoud may not specifically disclose the limitation(s) of the host is configured to: transfer data to the external memory device when a swap memory pool of the external memory device is available, and transfer data to the additional external memory device when the swap memory pool of the external memory device is unavailable.
Massiglia discloses wherein the host is configured to: transfer data to the external memory device when a swap memory pool of the external memory device is available, and transfer data to the additional external memory device when the swap memory pool of the external memory device is unavailable [Pages 84 – 91; The depth is a swap memory pool and as one swap memory pool is filled up another swap memory pool is used to store data on another memory device].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Massiglia in view of Microsoft in view of Daoud, because it allows data to be stored among multiple storage devices which improves I/O performance by allowing multiple pieces of data to be accessed in parallel [Normal Operation OF Stripped Disk Arrays, Page 85].
Regarding claim 18, Matturi teaches the host comprises a host processor [Paragraph 0016; A processor chipset is a processor in the host] having a cache corresponding to the main memory processing unit and the first memory processor [Paragraph 0016; Any memory in the host is considered cache including the memory used for the storage of compressed and uncompressed data in controller 106], an external memory device [110, Fig 1], additional external memory [131, Fig 1] disposed on a different board from the host [Paragraph 0031; The use of an interface to connect 131 to 105 shows memory 131 is on a separate board requiring an interface], compression of data [535, Fig 5], and decompression of data [560, Fig 5], and transferring data to multiple memory devices [540 and 575, Fig 5].
Daoud discloses any external memory device is configured to perform compression [210, Fig 2; 710 and 712, Fig 7; In step 710 the storage device received uncompressed data, compresses the uncompressed data, and then stores the compressed data].
However, Matturi in view of Microsoft in view of Daoud may not specifically disclose the limitation(s) of wherein the host is configured to: transfer data to the external memory device when a swap memory pool of the external memory device is available, and transfer data to the additional external memory device when the swap memory pool of the external memory device is unavailable.
Massiglia discloses wherein the host is configured to: transfer data to the external memory device when a swap memory pool of the external memory device is available, and transfer data to the additional external memory device when the swap memory pool of the external memory device is unavailable [Pages 84 – 91; The depth is a swap memory pool and as one swap memory pool is filled up another swap memory pool is used to store data on another memory device].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Massiglia in view of Microsoft in Matturi in view of Daoud, because it allows data to be stored among multiple storage devices which improves I/O performance by allowing multiple pieces of data to be accessed in parallel [Normal Operation OF Stripped Disk Arrays, Page 85].
Response to Arguments
Applicant's arguments filed 07/16/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 10 – 14 that the independent claim limitations are not taught by the prior art since Matturi fails to teach the amended limitations regarding what devices are one a board together and what devices are on different board. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The rejections have been updated due to the amendments and Microsoft is now used to teach the main memory device that is disposed on the first board with the host. Matturi additionally teaches an example of the external memory is a DIMM. A DIMM is contained on a separate printed circuit board than other devices in the system the DIMM is part of. This shows the external memory device (DIMM) is on a separate board than the first board the host is on.
The applicant argues on pages 14 – 15 that the dependent claim are allowed for being dependent on argued allowable base claims. After careful consideration of the applicant's arguments the examiner respectfully disagrees
The examiner has responded to the arguments regarding the base claims above. The rejections of the dependent claims are maintained based in part on the rejections of the base claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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