DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 5, 2026 has been entered.
Response to Amendment
The Amendment filed May 5, 2026 has been entered. Claims 1, 3-9, and 11-20 remain pending in the application. Claims 2 and 10 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, and 9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. (US 2019/0294350), Kim et al. (US 2024/0201879), and Fujiwara et al. (US 2005/0080874).
Regarding claim 1, Hahn et al. disclose:
A method, comprising:
allocating, from a random access memory of a memory sub-system ([0024] Host memory 160 may include, but is not limited to, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM)), a first buffer to buffer data (FIG. 2A Host memory buffer (HMB) 170; [0056] The host controller 180 has an HMB allocator 144, which may be configured to allocate the HMB to the memory controller 122. In one embodiment, the HMB allocator 144 is configured to make a static allocation of HMB 170 during initialization of the memory controller 122, and dynamic allocations of HMB 170 to the memory controller 122 during runtime; FIG. 3 step 304 Host controller allocates a portion of host memory for exclusive use [of the] memory controller) to be used during execution of commands communicated to the memory sub-system via a first submission queue from a host system (FIG. 2A Command submission queue 162; [0050] Commands to access the memory structure 126 in the memory die 108 may be placed by the host into a command submission queue 162);
retrieving, from the first submission queue, a command ([0065] A host queue manager 246 is configured to fetch and parse commands from the command submission queue 162);
…determining whether to change the first buffer according to the preferred size (FIG. 3 step 308 Memory controller requests the host for dynamic change in amount of host memory for exclusive use [of the] memory controller); and
changing the first buffer to the preferred size (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller);
maintaining a pool of free buffer units…wherein the free buffer units are allocated from the random access memory ([0052] A portion of the host memory 160 may be used for a host memory buffer (HMB) 170; [0024] Host memory 160 may include, but is not limited to, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM));
Hahn et al. do not appear to explicitly teach “determining a size of a data chunk used during execution of the command; determining a preferred size of the first buffer based on the size of the data chunk” and “…of a same predetermined size…wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.” However, Kim et al. disclose:
determining a size of a data chunk used during execution of the command (FIG. 2 step 220 Determine Unit of data required for one operation of resources of storage device based on access pattern of host device included in request);
determining a preferred size of the first buffer based on the size of the data chunk (FIG. 4);
Hahn et al. and Kim et al. are analogous art because Hahn et al. teach dynamic buffer allocation and Kim et al. teach operating resources of a storage device based on a memory access pattern.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn et al. and Kim et al. before him/her, to modify the teachings of Hahn et al. with the Kim et al. teachings of buffer allocation because allocating the size of the buffer based on the unit of data required for requested operation reduces the number of buffer allocations required and increases the speed of the storage device (Kim et al. [0078]).
Hahn et al. and Kim et al. do not appear to explicitly teach “…of a same predetermined size…wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.” However, Fujiwara et al. disclose:
…of a same predetermined size ([0037] the free-buffer pool 35…fixed-length (i.e., predetermined) memory buffers all having the same size)…
wherein the first buffer is implemented via concatenation of buffer units of the predetermined size ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
Hahn et al., Kim et al., and Fujiwara et al. are analogous art because Hahn et al. teach dynamic buffer allocation; Kim et al. teach operating resources of a storage device based on a memory access pattern; and Fujiwara et al. teach buffer allocation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn et al., Kim et al., and Fujiwara et al. before him/her, to modify the combine teachings of Hahn et al. and Kim et al. with the Fujiwara et al. teachings of concatenating buffer units of the predetermined size because doing so would create one larger buffer of a known size.
Regarding claim 3, Hahn et al. further disclose:
The method of claim 1, wherein the changing the first buffer includes (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller), in response to a decision to enlarge the first buffer to the preferred size ([0087] The memory controller 122 may request additional host memory 160 for exclusive use of the memory controller 122):
allocating one or more buffer units from the pool (FIG. 6 step 612 Host controller adds buffer(s) in host memory for exclusive use of memory controller); and
adding the one or more buffer units to the first buffer (FIG. 6 step 612)…
Hahn et al. and Kim et al. do not appear to explicitly teach “…through buffer concatenation.” However, Fujiwara et al. further disclose:
through buffer concatenation ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
Regarding claim 4, Hahn et al. further disclose:
The method of claim 1, wherein the changing the first buffer includes (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller), in response to a decision to reduce the first buffer to the preferred size ([0087] The memory controller 122 may request the host controller 180 to release some of the host memory 160 that was for the exclusive use of the memory controller 122):
removing one or more buffer units from the first buffer (FIG. 6 step 642 Host controller frees buffer(s) in host memory that were for exclusive use of memory controller); and
returning the one or more buffer units to the pool (FIG. 6 step 642).
Regarding claim 9, Hahn et al. disclose:
A memory sub-system, comprising:
a buffer memory configured to provide buffer units ([0052] A portion of the host memory 160 may be used for a host memory buffer (HMB) 170)…
a storage medium having a storage capacity accessible to a host system through commands communicated via a plurality of submission queues to the memory sub-system (FIG. 2A Command submission queue 162; [0050] Commands to access the memory structure 126 in the memory die 108 may be placed by the host into a command submission queue 162); and
a circuit (FIG. 2A Host Controller 180 and Front End Module 208 of Memory Controller 122 form a circuit) configured to:
allocate a first subset of the buffer units to form a first buffer to buffer data (FIG. 2A Host memory buffer (HMB) 170; [0056] The host controller 180 has an HMB allocator 144, which may be configured to allocate the HMB to the memory controller 122. In one embodiment, the HMB allocator 144 is configured to make a static allocation of HMB 170 during initialization of the memory controller 122, and dynamic allocations of HMB 170 to the memory controller 122 during runtime; FIG. 3 step 304 Host controller allocates a portion of host memory for exclusive use [of the] memory controller) for execution of commands communicated to the memory sub-system via a first submission queue from a host system (FIG. 2A Command submission queue 162);
retrieve, from the first submission queue, a command ([0065] A host queue manager 246 is configured to fetch and parse commands from the command submission queue 162);
…and
change the first buffer to the first size implemented (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller) via a second set of buffer units (FIG. 6 step 612 Host controller adds buffer(s) in host memory for exclusive use of memory controller); and
Hahn et al. do not appear to explicitly teach “…of a same predetermined size;…determine a size of a data chunk for execution of the command; determine a first size of the first buffer based on the size of the data chunk…track a pool of free buffer units of the predetermined size; wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.” However, Kim et al. disclose:
determine a size of a data chunk for execution of the command (FIG. 2 step 220 Determine Unit of data required for one operation of resources of storage device based on access pattern of host device included in request);
determine a first size of the first buffer based on the size of the data chunk (FIG. 4);
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Hahn et al. and Kim et al. do not appear to explicitly teach “…of a same predetermined size…track a pool of free buffer units of the predetermined size; wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.” However, Fujiwara et al. disclose:
…of a same predetermined size ([0037] the free-buffer pool 35…fixed-length (i.e., predetermined) memory buffers all having the same size)…
track a pool of free buffer units of the predetermined size ([0036] The free-buffer pool 35 is a pool of a plurality of available memory buffers; FIG. 4(b) Available-Buffer Size; [0047] the size of an available buffer is the total size of memory buffers included in the free-buffer pool 35);
wherein the first buffer is implemented via concatenation of buffer units of the predetermined size ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 11, Hahn et al. further disclose:
The memory sub-system of claim 9, wherein the circuit is configured to, in response to a decision to enlarge the first buffer to the first size ([0087] The memory controller 122 may request additional host memory 160 for exclusive use of the memory controller 122):
allocate, from the pool, one or more buffer units (FIG. 6 step 612 Host controller adds buffer(s) in host memory for exclusive use of memory controller); and
add the one or more buffer units to the first buffer (FIG. 6 step 612)…
Hahn et al. and Kim et al. do not appear to explicitly teach “…through buffer concatenation.” However, Fujiwara et al. further disclose:
through buffer concatenation ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
Regarding claim 12, Hahn et al. further disclose:
The memory sub-system of claim 9, wherein the circuit is configured to, in response to a decision to reduce the first buffer to the first size ([0087] The memory controller 122 may request the host controller 180 to release some of the host memory 160 that was for the exclusive use of the memory controller 122):
remove, from the first buffer, one or more buffer units (FIG. 6 step 642 Host controller frees buffer(s) in host memory that were for exclusive use of memory controller); and
return the one or more buffer units to the pool (FIG. 6 step 642).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al., Kim, and Fujiwara et al. et al. as applied to claim 1 above, and further is view of He et al. (US 2021/0073121).
Regarding claim 5, Hahn et al. further disclose:
The method of claim 1, further comprising:
…returning buffer units allocated to the first buffer to the pool (FIG. 6 step 642 Host controller frees buffer(s) in host memory that were for exclusive use of memory controller).
Hahn et al., Kim et al., and Fujiwara et al. do not appear to explicitly teach “determining that the first submission queue has been idling for a time period longer than a threshold.” However, He et al. disclose:
determining that the first submission queue has been idling for a time period longer than a threshold ([0028] To implement dynamic garbage collection workloads, the memory manager 125 is configured to record idle times for the memory device 110. In an example, an idle time is any time beyond a threshold in which a command queue for the memory controller 110 is empty. In an example, the threshold is ten milliseconds);
Hahn et al., Kim et al., Fujiwara et al., and He et al. are analogous art because Hahn et al. teach dynamic buffer allocation; Kim et al. teach operating resources of a storage device based on a memory access pattern; Fujiwara et al. teach buffer allocation; and He et al. teach command queues.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn et al., Kim et al., Fujiwara et al., and He et al. before him/her, to modify the combine teachings of Hahn et al., Kim et al., and Fujiwara et al. with the He et al. teachings of determining submission queue idleness because knowing when the memory device is not servicing access commands enables the system to efficiently perform background operations, such as garbage collection.
Regarding claim 13, Hahn et al. further disclose:
The memory sub-system of claim 9, wherein the circuit is further configured to:
…return buffer units allocated to the first buffer to the pool (FIG. 6 step 642 Host controller frees buffer(s) in host memory that were for exclusive use of memory controller).
Hahn et al., Kim et al., and Fujiwara et al. do not appear to explicitly teach “determine that the first submission queue has been idling for a time period longer than a threshold.” However, He et al. disclose:
determine that the first submission queue has been idling for a time period longer than a threshold ([0028] To implement dynamic garbage collection workloads, the memory manager 125 is configured to record idle times for the memory device 110. In an example, an idle time is any time beyond a threshold in which a command queue for the memory controller 110 is empty. In an example, the threshold is ten milliseconds);
The motivation for combining is based on the same rational presented for rejection of claim 5.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. (US 2019/0294350) and Kim et al. (US 2024/0201879).
Regarding claim 17, Hahn et al. disclose:
A non-transitory computer storage medium ([0051] non-transitory storage could be, for example, host memory 160, RAM 122b, memory structure 126, etc.) storing instructions which, when executed in a memory sub-system, cause the memory sub-system to perform a method ([0060] each module may include or comprise software stored in a processor readable device (e.g., host memory 160) to program one or more processors 150 to perform the functions described herein), comprising:
allocating, from a buffer memory of the memory sub-system ([0052] A portion of the host memory 160 may be used for a host memory buffer (HMB) 170), a first buffer to buffer data (FIG. 2A Host memory buffer (HMB) 170; [0056] The host controller 180 has an HMB allocator 144, which may be configured to allocate the HMB to the memory controller 122. In one embodiment, the HMB allocator 144 is configured to make a static allocation of HMB 170 during initialization of the memory controller 122, and dynamic allocations of HMB 170 to the memory controller 122 during runtime; FIG. 3 step 304 Host controller allocates a portion of host memory for exclusive use [of the] memory controller) to be used during execution of commands communicated to the memory sub-system via a first submission queue from a host system (FIG. 2A Command submission queue 162; [0050] Commands to access the memory structure 126 in the memory die 108 may be placed by the host into a command submission queue 162);
retrieving, from the first submission queue, a command ([0065] A host queue manager 246 is configured to fetch and parse commands from the command submission queue 162);…
changing a capacity of the first buffer (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller) based on the size of the data chunk (as taught by Kim et al. below).
Hahn et al. do not appear to explicitly teach “determining a size of a data chunk used during execution of the command; determining a preferred size of the first buffer based on the size of the data chunk.” However, Kim et al. disclose:
determining a size of a data chunk used during execution of the command (FIG. 2 step 220 Determine Unit of data required for one operation of resources of storage device based on access pattern of host device included in request); and
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn et al. and Kim et al. before him/her, to modify the teachings of Hahn et al. with the Kim et al. teachings of buffer allocation because allocating the size of the buffer based on the unit of data required for requested operation reduces the number of buffer allocations required and increases the speed of the storage device (Kim et al. [0078]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. and Kim et al. as applied to claim 1 above, and further in view of Fujiwara et al.
Regarding claim 18, Hahn et al. further disclose:
The non-transitory computer storage medium of claim 17, wherein the method further comprises:
maintaining a pool of free buffer units…wherein the free buffer units are allocated from the buffer memory ([0052] A portion of the host memory 160 may be used for a host memory buffer (HMB) 170; [0024] Host memory 160 may include, but is not limited to, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM));…
Hahn et al. and Kim et al. do not appear to explicitly teach “…of a same predetermined size…wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.” However, Fujiwara et al. disclose:
…of a same predetermined size ([0037] the free-buffer pool 35…fixed-length (i.e., predetermined) memory buffers all having the same size)…
wherein the first buffer is implemented via concatenation of buffer units of the predetermined size ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn et al., Kim et al., and Fujiwara et al. before him/her, to modify the combine teachings of Hahn et al. and Kim et al. with the Fujiwara et al. teachings of concatenating buffer units of the predetermined size because doing so would create one larger buffer of a known size.
Regarding claim 19, Hahn et al. further disclose:
The non-transitory computer storage medium of claim 18, wherein the changing the first buffer includes (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller), in response to a decision to enlarge the first buffer to the preferred size ([0087] The memory controller 122 may request additional host memory 160 for exclusive use of the memory controller 122):
allocating one or more buffer units from the pool (FIG. 6 step 612 Host controller adds buffer(s) in host memory for exclusive use of memory controller); and
adding the one or more buffer units to the first buffer (FIG. 6 step 612)…
Hahn et al. and Kim et al. do not appear to explicitly teach “…through buffer concatenation.” However, Fujiwara et al. further disclose:
through buffer concatenation ([0064] takes a predetermined number of memory buffers from the free-buffer pool 35 and concatenates the memory buffers to form a buffer 34).
Regarding claim 20, Hahn et al. further disclose:
The non-transitory computer storage medium of claim 19, wherein the changing the first buffer includes (FIG. 3 step 310 Host controller changes amount of host memory for exclusive us [of the] memory controller), in response to a decision to reduce the first buffer to the preferred size ([0087] The memory controller 122 may request the host controller 180 to release some of the host memory 160 that was for the exclusive use of the memory controller 122):
removing one or more buffer units from the first buffer (FIG. 6 step 642 Host controller frees buffer(s) in host memory that were for exclusive use of memory controller); and
returning the one or more buffer units to the pool (FIG. 6 step 642).
Allowable Subject Matter
Claims 6-8 and 14-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as discussed in the Non-Final Office Action mailed October 21, 2025.
Response to Arguments
Applicant's arguments filed May 5, 2026 have been fully considered but they are not persuasive. The rejection of claim 1 under 35 U.S.C. 103 as unpatentable over Hahn et al. and Kim et al. is determined to be proper and is, therefore, maintained.
Regarding the substance of the examiner's obviousness rejection as argued on pages 1-3 of the remarks, the requirements for obviousness are discussed in MPEP § 2142. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Applicant argues that the combination of Hahn et al., Kim et al., and Fujiwara fails to disclose the limitations “maintaining a pool of free buffer units of a same predetermined size, wherein the free buffer units are allocated from the random access memory; wherein the first buffer is implemented via concatenation of buffer units of the predetermined size” without pointing to how the cited references fail to teach the specific limitations.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant has failed to show how the combination of Hahn et al., Kim et al., and Fujiwara does not disclose the limitations “maintaining a pool of free buffer units of a same predetermined size, wherein the free buffer units are allocated from the random access memory; wherein the first buffer is implemented via concatenation of buffer units of the predetermined size.”
The rejection of claim 1 as obvious over Hahn et al. and Kim et al. is therefore maintained.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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