DETAILED ACTION
Response to Amendment
Examiner notes that the status identifier for claim 12 is “Currently Amended” but no changes to the claim have been presented.
MPEP 714 states “All claims being currently amended must be presented with markings to indicate the changes that have been made relative to the immediate prior version. The changes in any amended claim must be shown by strike-through (for deleted matter) or underlining (for added matter) with 2 exceptions: (1) for deletion of five or fewer consecutive characters, double brackets may be used (e.g., [[eroor]]); (2) if strike-through cannot be easily perceived (e.g., deletion of number "4" or certain punctuation marks), double brackets must be used (e.g., [[4]]). As an alternative to using double brackets, however, extra portions of text may be included before and after text being deleted, all in strike-through, followed by including and underlining the extra text with the desired change (e.g., number 4 as number 14 as ). An accompanying clean version is not required and should not be presented. Only claims of the status "currently amended" or "withdrawn" will include markings.”
Examiner has treated claim 12 as “Previously Presented.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-4, 11-13, 20 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Buxton et al. (U.S. Patent 6,473,280 cited in the Information Disclosure Statement filed December 9, 2024, hereafter Buxton).
Claim 2: Buxton teaches a method for protecting a system including a driver integrated circuit (Figure 1b), the method comprising:
generating a running delay metric (30) indicating delay (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) associated with one or more edges of a driver input signal (24’) in an output signal (Vout) at an output node of the driver integrated circuit coupled to a terminal of the driver integrated circuit (14), the running delay metric reflecting delay associated with a most recent edge of the driver input signal as well as delay associated with past edges of the driver input signal (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts, where the predetermined number of counts is the number of past edges of the driver input signal);
generating an error signal (FAIL) based on the running delay metric (24’ and 30 are inputs to counter 28); and
in response to the error signal, adjusting driving of the output signal externally to the driver integrated circuit (column 2 lines 6-14 where the powered circuit is turned off before additional failures occur).
Claim 3: Buxton further teaches generating the running delay metric includes generating a counter value indicative of an amount of delay (via counter 28).
Claim 4: Buxton further teaches that the counter value includes incrementing the counter value during delay intervals (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) and decrementing the counter value during non-delay intervals (the output of 30 will reset the counter to zero in an interval where IL1 transitions above and below threshold 36).
Claim 11: Buxton teaches a driver integrated circuit (Figure 1b) comprising:
a logic circuit (26, 28) configured to generate a running delay metric (30) indicating delay (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) associated with one or more edges a driver input signal are delayed in an output signal (between 24’ and Vout; column 4 lines 44-54), and to generate an error signal (FAIL) based on the running delay metric, the running delay metric reflecting delay associated with a most recent edge of the driver input signal as well as delay associated with past edges of the driver input signal (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts, where the predetermined number of counts is the number of past edges of the driver input signal); and
a driver circuit (20’) configured to drive the output signal to a terminal of the driver integrated circuit based on a driver input signal and the error signal (column 2 lines 6-14 where the powered circuit is turned off before additional failures occur).
Claim 12: Buxton further teaches that the logic circuit includes a counter circuit (28) configured to increment a counter value corresponding to an amount of delay, and generation of the error signal is based on the counter value (column 4 lines 44-54).
Claim 13: Buxton further teaches that the counter circuit is further configured to incrementing the counter value during delay intervals (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) and decrementing the counter value during non-delay intervals (the output of 30 will reset the counter to zero in an interval where IL1 transitions above and below threshold 36).
Claim 20: Buxton teaches an electronics system (Figure 1b) comprising:
a gate driver integrated circuit (Figure 1b) including a logic circuit (26, 28) configured to generate a running delay metric (30) indicating delay (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) associated with one or more edges a driver input signal are delayed in an output signal (between 24’ and Vout; column 4 lines 44-54), and to generate an error signal (FAIL) based on the running delay metric, the running delay metric reflecting delay associated with a most recent edge of the driver input signal as well as delay associated with past edges of the driver input signal (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts, where the predetermined number of counts is the number of past edges of the driver input signal); and
a drive transistor (MN1) coupled to the terminal of the gate driver integrated circuit to receive the output signal.
Claim 21: Buxton further teaches an isolation barrier and isolation communications channel (Figure 5 where 94’ provides PWM signals and is on a different power supply from 120; column 7 lines 51-56), the driver input signal received from the isolation communications channel (PWM).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buxton in view of Curbelo et al. (U.S. Patent 8,723,590 cited in the Information Disclosure Statement filed December 9, 2024, hereafter Curbelo).
Claims 5 and 14: Buxton teaches the limitations of claims 2 and 11 above. Buxton does not specifically teach that generating the error signal is based on an average of delay over time.
Curbelo teaches generating the indication of a delay (via 28 of Buxton) based on a counter value corresponding to an estimate of a long-term average of the delay over time (column 3 lines 7-12 and 55-63, where the estimate is of a long-term average of measured input and output signals of 28 of Buxton).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the long-term average of the delay as taught by Curbelo in the circuit of Buxton to provide efficient protection of the high power switch (column 1 lines 24-34 of Curbelo).
Claim(s) 6-9 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buxton in view of Nakatake et al. (U.S. Patent 7,948,277 cited in the Information Disclosure Statement filed December 9, 2024, hereafter Nakatake).
Claims 6 and 15: Buxton teaches the limitations of claims 2 and 11 above. Buxton does not specifically teach configuring an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the one or more indications.
Nakatake teaches configuring an output driver (3-5; Figure 1) to enter a safer output state (turn-off speed is adjusted to be lower) for a predetermined interval (column 7 lines 14-16) in response to detecting an error condition (from the abnormality detection circuit 7) based on the running delay metric (output of 28 of Buxton).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the safer output state taught by Nakatake in the circuit of Buxton to prevent erroneously detecting abnormalities (column 1 lines 34-39 of Nakatake).
Claims 7 and 16: The combined circuit further teaches that driving the output signal further includes transitioning from the safer output state to a normal state in response to expiration of the predetermined interval in the safer output state (column 8 lines 20-27 of Nakatake).
Claims 8 and 17: The combined circuit further teaches that the output driver is configured to transition to the safer output state from a second safer output state (column 8 lines 15-19 of Nakatake where the gate voltage has not fallen below the predetermined voltage but an “ON” command is detected) and in response to a second expiration of a second predetermined interval in the second safer output state (sampling period T1 of Nakatake; column 8 lines 12-15), and driving the output signal further includes transitioning to the second safer output state from a normal output state (gate turn-off signal is still applied; column 8 lines 15-19 of Nakatake).
Claims 9 and 18: The combined circuit further teaches that in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time (column 4 lines 15-29 of Nakatake where the turn-off speed is adjusted).
Claim(s) 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buxton in view of Cortigiani et al. (U.S. Patent Application Publication 2014/0077782 cited in the Information Disclosure Statement filed December 9, 2024, hereafter Cortigiani).
Claims 10 and 19: Buxton teaches the limitations of claims 2 and 11 above. Buxton does not specifically teach generating an indication of a sensed temperature.
Cortigiani teaches an output signal (OUT; Figure 1 corresponding to 14 of Buxton) driven further based on an indication of a sensed temperature of a die of the driver integrated circuit (Figure 3); and
configuring an output driver to enter a safer output state in response to the indication of the sensed temperature exceeding a predetermined threshold (state C; Figure 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the indication of a sensed temperature taught by Cortigiani in the circuit of Buxton to detect faulty or undesired modes of operation ([0018] of Cortigiani).
Response to Arguments
Applicant's arguments filed February 9, 2026 have been fully considered but they are not persuasive.
Applicant asserts that Buxton does not teach generating a running delay metric indicating delay associated with one or more edges of a driver input signal. Examiner respectfully disagrees. Buxton teaches generating a running delay metric (30) indicating delay (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts) associated with one or more edges of a driver input signal (24’) in an output signal (Vout) at an output node of the driver integrated circuit coupled to a terminal of the driver integrated circuit (14), the running delay metric reflecting delay associated with a most recent edge of the driver input signal as well as delay associated with past edges of the driver input signal (column 4 lines 44-54 where 28 will indicate a FAIL on 32 if the counter is not reset for a predetermined number of counts, where the predetermined number of counts is the number of past edges of the driver input signal).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O/Examiner, Art Unit 2836 /Menatoallah Youssef/SPE, Art Unit 2836
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