DETAILED ACTION
This Office Action is in response to the Application filed 26 August 2024. Claims 1-11 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation " the second opening" in Line 9 of the claim. There is insufficient antecedent basis for this limitation in the claim. The second opening has a basis in Claim 1, however Claim 11 is independent and cannot claim antecedent basis from Claim 1.
Furthermore, there is no first opening claimed in Claim 11.
For purposes of examination, “the second opening” will be treated as reciting “the gate opening” since these represent equivalent portions of the device in different claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez et. al (Us 2020/0091285 A1) in view of Then et. al (US 2019/0189611 A1)
Regarding Claim 1, Hafez discloses (as shown in Figs. 8A-H) A production method ([0015] FIG. 8A-8H are cross-sectional views of III-N MISFET structures as selected operations of the methods illustrated in FIG. 7 are performed) for a semiconductor device, the production method comprising:
forming a first nitride semiconductor layer ([0031] III-N material 305 is a binary alloy (e.g., GaN, AlN, InN)) having nitrogen polarity at an upper surface thereof; ([0033] Periodic table. III-N material 310 may be any III-N material known to be suitable as a polarization material for III-N material 305. III-N material 310 may comprise any alloy distinct from that of III-N material 305 so as to modulate the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N materials)
forming a first dielectric film ([0038] dielectric materials 330) on the first nitride semiconductor layer (305); ([0053] III-N materials 310 and 305 have been patterned into features (e.g., mesas or islands) with dielectric material(s) 330 between and over the III-N material features)
forming a first opening in the first dielectric film (330), a part of the first nitride semiconductor layer (305) being exposed from the first opening; ([0054] In the example shown in FIG. 8B, a patterning process is employed to form openings through dielectric material 330 and expose portions of III-N material 310…III-N material 305 may be similarly etched (e.g., with any wet chemical or dry etch process known to be suitable), for example to reveal a sidewall that intersects 2DEG 312)
forming a second nitride semiconductor layer ([0034] MISFET structure 301 further includes a source 320 and a drain 325) ([0035] For example, source and drain 320, 325 may both be InGaN) inward of the first opening and on the first nitride semiconductor layer (305); ([0054] Source and drain semiconductor material, such as any of those described above, may then be deposited or epitaxial grown within the source and drain openings to arrive at the structure illustrated in FIG. 8B.)
forming a second opening ([0055] recesses 830) in the first dielectric film (330) after the formation of the second nitride semiconductor layer (320, 325), ([0055] As further shown in FIG. 8C, recesses 830 have been formed through a dielectric material 830, through dielectric material(s) 330, and through a partial thickness of III-N material 310)
a part of the first nitride semiconductor layer (305) being exposed from the second opening (830); (See Fig. 8C, showing III-N material 305 exposed through recess 830)
forming a second dielectric film ([0034] gate dielectric stack that comprises both a first gate dielectric material 331, and a second gate dielectric material 332) inward of the second opening (830) and on the first nitride semiconductor layer (305); (See Fig. 8D, showing first gate dielectric layer 331 in the recess 830, and on the III-N material 305)
and forming a gate electrode ([0037] Gate electrode 315) above the second opening (830) and on the second dielectric film (331). ([0037] Gate electrode 315 is located within a recess in the underlying III-N material that extends a depth (e.g., z-dimension) through at least a partial thickness of III-N material 310)
However, Hafez fails to disclose forming an ohmic electrode that is in an ohmic contact with the second nitride semiconductor layer (320, 325).
Then discloses (as shown in Fig. 2O) forming an ohmic electrode ([0083] formation of a source contact 248A on the raised source structure 228A and drain contact 248B on the raised drain structure 228B to form a III-N transistor 201) that is in an ohmic contact with the second nitride semiconductor layer ([0072] formation of a raised source structure 228A and a raised drain structure 228B)
Then teaches that the source and drain contacts (248A-B) are formed in order to form the transistor. ([0083] FIG. 2O illustrates the structure of FIG. 2N, following the formation of a source contact 248A on the raised source structure 228A and drain contact 248B on the raised drain structure 228B to form a III-N transistor 201) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the source/drain contacts of Then with the device in Hafez in order to form a transistor.
Regarding Claim 6, Hafez further discloses (as shown in Figs. 8A-H) the second dielectric film (331, 332) includes at least one selected from the group consisting of a silicon nitride film, an aluminum oxide film, and a silicon oxynitride film. ([0040] In some such embodiments, gate dielectric material 331 comprises both aluminum and oxygen (e.g., Al.sub.2O.sub.3), or comprises both hafnium and oxygen (e.g. HfO.sub.x)… In some such embodiments, gate dielectric material 332 comprises both silicon and oxygen (e.g., SiO.sub.2). In some other embodiments, gate dielectric material 332 comprises both silicon and nitrogen (e.g., Si.sub.3N.sub.4). In some exemplary embodiments where gate dielectric material 331 is a metal oxide, gate dielectric material 332 comprises silicon and at least one of oxygen or nitrogen.)
Regarding Claim 8, Hafez discloses (as shown in Figs. 8A-H) a semiconductor device comprising:
a first nitride semiconductor layer ([0031] III-N material 305 is a binary alloy (e.g., GaN, AlN, InN)) having nitrogen polarity at an upper surface thereof; ([0033] Periodic table. III-N material 310 may be any III-N material known to be suitable as a polarization material for III-N material 305. III-N material 310 may comprise any alloy distinct from that of III-N material 305 so as to modulate the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N materials)
a first dielectric film ([0038] dielectric materials 330) on the first nitride semiconductor layer (305); ([0053] III-N materials 310 and 305 have been patterned into features (e.g., mesas or islands) with dielectric material(s) 330 between and over the III-N material features)
a first opening ([0054] In the example shown in FIG. 8B, a patterning process is employed to form openings through dielectric material 330 and expose portions of III-N material 310…III-N material 305 may be similarly etched (e.g., with any wet chemical or dry etch process known to be suitable), for example to reveal a sidewall that intersects 2DEG 312) and a second opening ([0055] recesses 830) in the first dielectric film (330), a part of the first nitride semiconductor layer (305) being exposed from the first opening; ([0054] In the example shown in FIG. 8B, a patterning process is employed to form openings through dielectric material 330 and expose portions of III-N material 310…III-N material 305 may be similarly etched (e.g., with any wet chemical or dry etch process known to be suitable), for example to reveal a sidewall that intersects 2DEG 312) in the first dielectric film
a second nitride semiconductor layer ([0034] MISFET structure 301 further includes a source 320 and a drain 325) ([0035] For example, source and drain 320, 325 may both be InGaN) that is inward of the first opening and on the first nitride semiconductor layer (305); ([0054] Source and drain semiconductor material, such as any of those described above, may then be deposited or epitaxial grown within the source and drain openings to arrive at the structure illustrated in FIG. 8B.)
a second dielectric film ([0034] gate dielectric stack that comprises both a first gate dielectric material 331…, and a second gate dielectric material 332) that is inward of the second opening (830) and on the first nitride semiconductor layer (305); (See Fig. 8D, showing first gate dielectric layer 331 in the recess 830, and on the III-N material 305)
and a gate electrode ([0037] Gate electrode 315) that is above the second opening (830) and on the second dielectric film (331). ([0037] Gate electrode 315 is located within a recess in the underlying III-N material that extends a depth (e.g., z-dimension) through at least a partial thickness of III-N material 310)
However, Hafez fails to disclose an ohmic electrode that is in an ohmic contact with the second nitride semiconductor layer (320, 325).
Then discloses (as shown in Fig. 2O) an ohmic electrode ([0083] formation of a source contact 248A on the raised source structure 228A and drain contact 248B on the raised drain structure 228B to form a III-N transistor 201) that is in an ohmic contact with the second nitride semiconductor layer ([0072] formation of a raised source structure 228A and a raised drain structure 228B)
Then teaches that the source and drain contacts (248A-B) are formed in order to form the transistor. ([0083] FIG. 2O illustrates the structure of FIG. 2N, following the formation of a source contact 248A on the raised source structure 228A and drain contact 248B on the raised drain structure 228B to form a III-N transistor 201) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the source/drain contacts of Then with the device in Hafez in order to form a transistor.
Regarding Claim 9, Hafez further discloses (as shown in Figs. 8A-H) wherein the first dielectric film is silicon nitride ([0038] In some examples, dielectric material(s) 330 includes silicon and nitrogen (e.g., silicon oxynitrides or silicon nitride).)
where the second dielectric film is Aluminum oxide ([0040] In some exemplary embodiments, gate dielectric material 331 is a metal oxide (i.e., comprises at least one metal and oxygen). In some such embodiments, gate dielectric material 331 comprises both aluminum and oxygen (e.g., Al.sub.2O.sub.3), or comprises both hafnium and oxygen (e.g. HfO.sub.x))
However, Hafez fails to disclose wherein a specific resistance of the second dielectric film (331) is higher than that of the first dielectric film (330).
It would have been obvious to a person having ordinary skill in the art before the effective filing date to have a specific resistance of the second dielectric film (331) is higher than that of the first dielectric film (330) based on the disclosure of Hafez. Hafez teaches multiple materials for the first dielectric film (330) including SiN. Hafez further teaches several materials for the second dielectric layer (331), including Al2O3. Therefore, it would have been obvious to have the first dielectric film (330) be SiN. and the second dielectric layer (331) be Al2O3. This would result in the specific resistance of the second dielectric film (331) is higher than that of the first dielectric film (330).
Regarding Claim 10, Hafez further discloses (as shown in Figs. 8A-H) a dielectric constant of the second dielectric film (331) is higher than that of the first dielectric film (330). ([0038] In some examples, dielectric material(s) 330 includes silicon and oxygen (e.g., silicon oxides or silicon oxynitrides).) ([0040] In some embodiments, gate dielectric material 331 is a dielectric material that provides a good interface with III-N material 310 and/or III-N material 305. In some exemplary embodiments, gate dielectric material 331 is a metal oxide (i.e., comprises at least one metal and oxygen). In some such embodiments, gate dielectric material 331 comprises both aluminum and oxygen (e.g., Al.sub.2O.sub.3), or comprises both hafnium and oxygen (e.g. HfO.sub.x).)
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez in view of Then as applied to claim 1 above, and further in view of Gong et. al (Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1-x films by surface sol-gel method and reaction-anneal treatment).
Regarding Claim 2, Hafez further discloses (as shown in Figs. 8A-H) the formation of the second dielectric film includes: forming a plurality of insulating films ([0034] gate dielectric stack that comprises both a first gate dielectric material 331…, and a second gate dielectric material 332) on the first nitride semiconductor layer (305); (See Fig. 8D, showing first gate dielectric layer 331 in the recess 830, and on the III-N material 305)
However, Hafez in view of Than fails to disclose performing a thermal treatment on the plurality of insulating films, thereby forming a composite insulating film.
Gong discloses performing a thermal treatment on the plurality of insulating films, thereby forming a composite insulating film. ([Col. 2 Line 25- Col. 3 Line2] To fabricate ultrathin (HfO2)x(SiO2)1−x films, the reaction-anneal treatment of as-deposited HfO2 films were performed in nitrogen atmosphere at various temperatures from 500 to 700 °C for 5 min by rapid thermal anneal (RTA).)
Gong teaches than hafnium-silicate films have better thermal stability than hafnium oxide films. ([Col. 1 Lines 11-13] In recent years, Hf–silicate has attracted considerable attention due to its better thermal stability and more preferable interface on Si) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to perform a thermal treatment on the stacked dielectric films in order to form a composite film in order to increase thermal stability.
Regarding Claim 3, Hafez further discloses (as shown in Figs. 8A-H) the plurality of insulating films (331, 332) include:
a first oxide film including at least one selected from the group consisting of hafnium, lanthanum, and zirconium; ([0040] gate dielectric material 331 comprises both aluminum and oxygen (e.g., Al.sub.2O.sub.3), or comprises both hafnium and oxygen (e.g. HfO.sub.x))
and a second oxide film including at least one selected from the group consisting of silicon and aluminum. ([0040] In some such embodiments, gate dielectric material 332 comprises both silicon and oxygen (e.g., SiO.sub.2))
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez in view of Then and Gong as applied to claim 2 above, and further in view of Shin (US 2009/0140354 A1) and Jeon et. al (Performance of nitride Hf-silicate high-K gate dielectrics).
Regarding Claim 4, Hafez in view of Then and Gong fails to disclose the formation of the second dielectric film includes nitriding the composite insulating film after performing the thermal treatment.
Shin discloses a dielectric film that includes nitriding the composite insulating film after forming the hafnium silicon oxynitride layer. ([0009] forming a silicon oxynitride (SiON) layer and a hafnium silicon oxynitride (HfSiON) layer by performing a nitrogen plasma process on the semiconductor substrate including the silicon oxide (SiOx) layer and the hafnium silicate (HfSiO) layer, forming a polysilicon layer on the hafnium silicon oxynitride (HfSiON) layer)
Jeon teaches that hafnium silicon oxynitride has better thermal stability than hafnium silicon oxide. ([Col. 1 Lines 56-59] However, HfSiON showed lower thermal sensitivity (lower electrical thickness increase) indicating better thermal stability as compared to HfSiO) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the nitriding process of Shin in Hafez in view of Then and Gong in order to change the hafnium silicon oxide into hafnium silicon oxynitride in order to improve thermal stability. Furthermore, it would have been obvious to a person having ordinary skill in the art to perform the nitriding after the thermal treatment in Hafez in view of Then and Gong since the thermal treatment forms the hafnium silicon oxide in Hafez in view of Then and Gong.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez in view of Then as applied to claim 1 above, and further in view of Okita et. al (US 026/0164731 A1) and Liu et. al (Improving Performance and Breakdown Voltage in Normally-Off GaN Recessed Gate MIS-HEMTs Using Atomic Layer Etching and Gate Field Plate for High-Power Device Applications)
Regarding Claim 5, Hafez in view of Then fails to disclose between the formation of the second opening (830) and the formation of the second dielectric film (331,332), reducing the part of the first nitride semiconductor layer (305) exposed from the second opening (830) using thermally decomposed ammonia.
Okita discloses (as shown in Figs. 18A-F) reducing the part of the first nitride semiconductor layer ([0094] first nitride semiconductor layer 3 (for example, a single layer or a plurality of layers of Group III nitride semiconductors such as InGaN, InN, AlGaN, and AlInGaN) including GaN is formed) exposed from the second opening ([0104] Then, resist pattern 16 is formed by a known lithography method, and gate recess 15 is formed by dry etching using an inductively coupled plasma reactive ion etching (ICP-RIE) method or the like (FIG. 18C)) using thermally decomposed ammonia. ([0120] In order to activate the n-type impurity in the nitride semiconductor and to form diffusion region 14 around damaged region 13, the activation annealing is usually performed at 1100° C. or more, preferably 1150° C. or more for about 1 to 30 minutes.) ([0121] When the in-situ activation annealing described above is performed … second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia, and thus gate recess 15 is deeper.)
Okita teaches that the etching of the second nitride layer 4 is carried out during the in-situ activation. ([0121] When the in-situ activation annealing described above is performed … second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia, and thus gate recess 15 is deeper.) Okita further teaches that the in-situ activation occurs at more than 1100° C. ([0120] In order to activate the n-type impurity in the nitride semiconductor and to form diffusion region 14 around damaged region 13, the activation annealing is usually performed at 1100° C. or more, preferably 1150° C. or more for about 1 to 30 minutes.) At this temperature, Ammonia decomposes due to the heat. Hence the etching done by the ammonia gas ([0121] second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia) is performed by thermally decomposed ammonia.
Liu teaches that recessing the gate in an HEMT provides a larger gate swing, higher VTH, and lower gate leakage. ([Page 2 Line 13-14] the implementation of the recessed gate GaN MIS-HEMT is more widely considered as it provides a larger gate swing, higher VTH, and lower gate leakage. ) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date pf the application to recess the gate in Hafez in view of Then by the process described in Okita in order to provides a larger gate swing, higher VTH, and lower gate leakage.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez in view of Then as applied to claim 1 above, and further in view of Deng et. al (Suppression and Characterization of interface states at low-pressure-chemical-vapor-deposited SiNx/III-nitride heterostructures).
Regarding Claim 7, Hafez further discloses where the first dielectric film (330) is silicon nitride. ([0038] In some examples, dielectric material(s) 330 includes silicon and nitrogen (e.g., silicon oxynitrides or silicon nitride))
Hafez in view of Then fails to disclose wherein the first dielectric film (330) is formed by a thermal film forming method using a raw material including nitrogen.
Deng discloses that silicon nitride in GaN MIS-FETs are made a thermal film forming method (Abstract Lines 1-2] Silicon nitride (SiNx) grown by low-pressure chemical vapor deposition (LPCVD) at a reduced growth temperature (650 °C), is utilized for fabrication of GaN metal–insulator-semiconductor (MIS) power devices.)
Deng further discloses the thermal film forming method uses a raw material including nitrogen ([Col. 3 Lines 38-39] The gas flow rate of SiH2Cl2 and NH3 are 12 and 100 sccm)
Deng teaches that using LPCVD to form the SiN layer avoids plasma-induced damages caused by PECVD. ([Col. 1 Lines 6-11] Some previous studies reported that the SiNx film grown by the low pressure chemical vapor deposition (LPCVD) is an attractive dielectric for GaN-based power devices because of the LPCVD’s plasma-free feature, so that plasma-induced damages to GaN can be avoided compared with the plasma enhanced chemical vapor deposition (PECVD) method.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to form the first dielectric layer (330) in Hafez in view of Then by LPCVD in order to avoid plasma induced damages.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hafez and further in view of Okita et. al (US 026/0164731 A1) and Liu et. al (Improving Performance and Breakdown Voltage in Normally-Off GaN Recessed Gate MIS-HEMTs Using Atomic Layer Etching and Gate Field Plate for High-Power Device Applications)
Regarding Claim 11, Hafez discloses (as shown in Figs. 8A-H) A production method ([0015] FIG. 8A-8H are cross-sectional views of III-N MISFET structures as selected operations of the methods illustrated in FIG. 7 are performed) for a semiconductor device, the production method comprising:
forming a first nitride semiconductor layer ([0031] III-N material 305 is a binary alloy (e.g., GaN, AlN, InN)) having nitrogen polarity at an upper surface thereof; ([0033] Periodic table. III-N material 310 may be any III-N material known to be suitable as a polarization material for III-N material 305. III-N material 310 may comprise any alloy distinct from that of III-N material 305 so as to modulate the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N materials)
forming a first dielectric film ([0038] dielectric materials 330) on the first nitride semiconductor layer (305); ([0053] III-N materials 310 and 305 have been patterned into features (e.g., mesas or islands) with dielectric material(s) 330 between and over the III-N material features)
forming a gate opening ([0055] recesses 830) in the first dielectric film (330) after the formation of the second nitride semiconductor layer (320, 325), ([0055] As further shown in FIG. 8C, recesses 830 have been formed through a dielectric material 830, through dielectric material(s) 330, and through a partial thickness of III-N material 310)
a part of the first nitride semiconductor layer (305) being exposed from the gate opening (830); (See Fig. 8C, showing III-N material 305 exposed through recess 830)
and forming a second dielectric film ([0034] gate dielectric stack that comprises both a first gate dielectric material 331, and a second gate dielectric material 332) inward of the gate opening (830) and on the first nitride semiconductor layer (305); (See Fig. 8D, showing first gate dielectric layer 331 in the recess 830, and on the III-N material 305)
However, Hafez fails to disclose reducing the part of the first nitride semiconductor layer (305) exposed from the gate opening (830) using thermally decomposed ammonia. ([0121] When the in-situ activation annealing described above is performed before the formation of third nitride semiconductor layer 17, and second nitride semiconductor layer 4 includes, for example, GaN which does not contain Al, second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia, and thus gate recess 15 is deeper.)
Okita discloses (as shown in Figs. 18A-F) reducing the part of the first nitride semiconductor layer ([0094] first nitride semiconductor layer 3 (for example, a single layer or a plurality of layers of Group III nitride semiconductors such as InGaN, InN, AlGaN, and AlInGaN) including GaN is formed) exposed from the gate opening ([0104] Then, resist pattern 16 is formed by a known lithography method, and gate recess 15 is formed by dry etching using an inductively coupled plasma reactive ion etching (ICP-RIE) method or the like (FIG. 18C)) using decomposed ammonia.
Okita discloses (as shown in Figs. 18A-F) reducing the part of the first nitride semiconductor layer ([0094] first nitride semiconductor layer 3 (for example, a single layer or a plurality of layers of Group III nitride semiconductors such as InGaN, InN, AlGaN, and AlInGaN) including GaN is formed) exposed from the second opening ([0104] Then, resist pattern 16 is formed by a known lithography method, and gate recess 15 is formed by dry etching using an inductively coupled plasma reactive ion etching (ICP-RIE) method or the like (FIG. 18C)) using thermally decomposed ammonia. ([0120] In order to activate the n-type impurity in the nitride semiconductor and to form diffusion region 14 around damaged region 13, the activation annealing is usually performed at 1100° C. or more, preferably 1150° C. or more for about 1 to 30 minutes.) ([0121] When the in-situ activation annealing described above is performed … second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia, and thus gate recess 15 is deeper.)
Okita teaches that the etching of the second nitride layer 4 is carried out during the in-situ activation. ([0121] When the in-situ activation annealing described above is performed … second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia, and thus gate recess 15 is deeper.) Okita further teaches that the in-situ activation occurs at more than 1100° C. ([0120] In order to activate the n-type impurity in the nitride semiconductor and to form diffusion region 14 around damaged region 13, the activation annealing is usually performed at 1100° C. or more, preferably 1150° C. or more for about 1 to 30 minutes.) At this temperature, Ammonia decomposes due to the heat. Hence the etching done by the ammonia gas ([0121] second nitride semiconductor layer 4 at the bottom surface of gate recess 15 is etched by a carrier gas such as hydrogen and a raw material gas such as ammonia) is performed by thermally decomposed ammonia.
Liu teaches that recessing the gate in an HEMT provides a larger gate swing, higher VTH, and lower gate leakage. ([Page 2 Line 13-14] the implementation of the recessed gate GaN MIS-HEMT is more widely considered as it provides a larger gate swing, higher VTH, and lower gate leakage. ) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date pf the application to recess the gate in Hafez in view of Then by the process described in Okita in order to provides a larger gate swing, higher VTH, and lower gate leakage.
Conclusion
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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