Prosecution Insights
Last updated: October 02, 2026
Application No. 18/815,225

RESOURCE ELEMENT OVERLAP BETWEEN A SYNCHRONIZATION SIGNAL BLOCK AND DEMODULATION REFERENCE SIGNAL

Non-Final OA §DP
Filed
Aug 26, 2024
Priority
May 11, 2021 — provisional 63/187,293 +1 more
Examiner
AJID, ABDELTIF
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
288 granted / 375 resolved
+16.8% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
15 currently pending
Career history
394
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
64.1%
+24.1% vs TC avg
§102
23.9%
-16.1% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619(CCPA1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. - Claim 2-31 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over of US patent US12108351B2 for the parent application 17740881. Claim# Present application 18815225 US patent US12108351B2 for the parent application 17740881 Claim # 2 2. (New) An apparatus for wireless communications at a user equipment (UE), comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the UE to: receive a synchronization signal block associated with a physical layer cell identifier, wherein one or more first resource elements carrying the synchronization signal block overlap with one or more second resource elements carrying a downlink shared channel associated with the physical layer cell identifier; and process a demodulation reference signal corresponding to the downlink shared channel in accordance with the synchronization signal block and the downlink shared channel being associated with the physical layer cell identifier, wherein, in accordance with the physical layer cell identifier, no overlap is permitted between the one or more first resource elements and the one or more second resource elements 1. An apparatus for wireless communications at a user equipment (UE), comprising: a processor; memory coupled with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: receive a synchronization signal block associated with a first physical layer cell identifier, wherein one or more resource elements carrying the synchronization signal block overlap with one or more resource elements carrying a downlink shared channel associated with a second physical layer cell identifier; determine, according to a comparison of the first physical layer cell identifier and the second physical layer cell identifier, whether overlap is permitted between the one or more resource elements carrying the synchronization signal block and one or more resource elements carrying a demodulation reference signal corresponding to the downlink shared channel; and process the demodulation reference signal based at least in part on the determination. 2. The apparatus of claim 1, wherein the instructions to determine whether overlap is permitted are executable by the processor to cause the apparatus to: determine that no overlap is permitted between the one or more resource elements carrying the synchronization signal block and the one or more resource elements carrying the demodulation reference signal based at least in part on the first physical layer cell identifier and the second physical layer cell identifier being a same physical layer cell identifier. 1+2 10 18 10. (New) An apparatus for wireless communications at a network entity, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the network entity to: transmit a synchronization signal block associated with a physical layer cell identifier, wherein one or more first resource elements carrying the synchronization signal block overlap with one or more second resource elements carrying a downlink shared channel associated with the physical layer cell identifier; and process a demodulation reference signal corresponding to the downlink shared channel in accordance with the synchronization signal block and the downlink shared channel being associated with the physical layer cell identifier, wherein, in accordance with the physical layer cell identifier, no overlap is permitted between the one or more first resource elements and the one or more second resource elements. 18. (New) A method for wireless communication by a user equipment (UE), comprising: receiving a synchronization signal block associated with a physical layer cell identifier, wherein one or more first resource elements carrying the synchronization signal block overlap with one or more second resource elements carrying a downlink shared channel associated with the physical layer cell identifier; and processing a demodulation reference signal corresponding to the downlink shared channel in accordance with the synchronization signal block and the downlink shared channel being associated with the physical layer cell identifier, wherein, in accordance with the physical layer cell identifier, no overlap is permitted between the one or more first resource elements and the one or more second resource elements. 26. (New) A method for wireless communication by a network entity, comprising: transmitting a synchronization signal block associated with a physical layer cell identifier, wherein one or more first resource elements carrying the synchronization signal block overlap with one or more second resource elements carrying a downlink shared channel associated with the physical layer cell identifier; and processing a demodulation reference signal corresponding to the downlink shared channel in accordance with the synchronization signal block and the downlink shared channel being associated with the physical layer cell identifier, wherein, in accordance with the physical layer cell identifier, no overlap is permitted between the one or more first resource elements and the one or more second resource elements. 13. An apparatus for wireless communications at a network entity, comprising: a processor; memory coupled with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: transmit a synchronization signal block associated with a first physical layer cell identifier, wherein one or more resource elements carrying the synchronization signal block overlap with one or more resource elements carrying a downlink shared channel associated with a second physical layer cell identifier; determine, according to a comparison of the first physical layer cell identifier and the second physical layer cell identifier, whether overlap is permitted between the one or more resource elements carrying the synchronization signal block and one or more resource elements carrying a demodulation reference signal corresponding to the downlink shared channel; and process the demodulation reference signal based at least in part on the determination. 14. The apparatus of claim 13, wherein the instructions are further executable by the processor to cause the apparatus to: determine there is no overlap between the one or more resource elements carrying the synchronization signal block and the one or more resource elements carrying the demodulation reference signal based at least in part on the first physical layer cell identifier and the second physical layer cell identifier being a same physical layer cell identifier. 25. A method for wireless communications at a user equipment (UE), comprising: receiving a synchronization signal block associated with a first physical layer cell identifier, wherein one or more resource elements carrying the synchronization signal block overlap with one or more resource elements carrying a downlink shared channel associated with a second physical layer cell identifier; determining, according to a comparison of the first physical layer cell identifier and the second physical layer cell identifier, whether overlap is permitted between the one or more resource elements carrying the synchronization signal block and one or more resource elements carrying a demodulation reference signal corresponding to the downlink shared channel; and processing the demodulation reference signal based at least in part on the determination. 26. The method of claim 25, wherein determining whether overlap is permitted comprises: determining that no overlap is permitted between the one or more resource elements carrying the synchronization signal block and the one or more resource elements carrying the demodulation reference signal based at least in part on the first physical layer cell identifier and the second physical layer cell identifier being a same physical layer cell identifier. 30. A method for wireless communications at a network entity, comprising: transmitting a synchronization signal block associated with a first physical layer cell identifier, wherein one or more resource elements carrying the synchronization signal block overlap with one or more resource elements carrying a downlink shared channel associated with a second physical layer cell identifier; determining, according to a comparison of the first physical layer cell identifier and the second physical layer cell identifier, whether overlap is permitted between the one or more resource elements carrying the synchronization signal block and one or more resource elements carrying a demodulation reference signal corresponding to the downlink shared channel; and processing the demodulation reference signal based at least in part on the determination. 13+14 25+26 The claims 3;4;5;6 ;7have the double patenting with the claims 6;7;9;11;2, respectively. US patent US12108351B2 for the parent application 17740881discloses claims 8 and 9 in (Col 8 lines 49-61). Thus, the claims of US patent US12108351B2 for the parent application 17740881 contain every element of the claims, of the instant application and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELTIF AJID whose telephone number is (571)272-7749. The examiner can normally be reached 9 am -5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Avellino can be reached at (571)272-3905. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABDELTIF AJID/ Primary Examiner, Art Unit 2478
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Prosecution Timeline

Aug 26, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+12.3%)
3y 1m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allowance rate.

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