Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Applicant claimed for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in parent Application.
2. Claims 1-18 is presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
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4. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12080354. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-10 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells, the method comprising: performing an erase operation upon receipt of an erase command, the erase operation including: a plurality of erase voltage apply steps applied to the first part of the memory cells and the second part of the memory cells; a plurality of erase verify steps applied to the first part of the memory cells and the second part of the memory cells, the erase verify steps each performed after a corresponding one of the erase voltage apply steps; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step; suspending the erase operation upon receipt of a suspend command during performing one of the erase voltage apply steps, the erase operation being suspended at completion of one of the erase voltage apply steps; performing a first operation upon receipt of a first command, an operation time of the erase operation being longer than an operation time of the first operation; and resuming the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells wherein the memory controller: sends an erase command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to perform an erase operation, the erase operation including: a plurality of erase voltage apply steps applied to the first part of the memory cells and the second part of the memory cells; a plurality of erase verify steps applied to the first part of the memory cells and the second part of the memory cells, the erase verify steps each performed after a corresponding one of the erase voltage apply steps; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step; sends a suspend command to the nonvolatile semiconductor memory device during performing one of the erase voltage apply steps to instruct the nonvolatile semiconductor memory device to suspend the erase operation, the erase operation being suspended at completion of one of the erase voltage apply steps; sends a first command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to perform a first operation, an operation time of the erase operation being longer than an operation time of the first operation; and sends a resume command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
5. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 11664077. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-9 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, corresponding one of the erase voltage apply steps;
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1-9 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and device during performing one of the erase voltage apply steps to instruct the nonvolatile semiconductor memory device to suspend the erase operation, the erase operation being suspended at completion of one of the erase voltage apply steps; sends a first command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to perform a first operation, an operation time of the erase operation being longer than an operation time of the first operation; and sends a resume command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
6. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 11062777. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-11 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, an operation time of the first operation; and resuming the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1-11 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
7. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2, 5-6 and 8 of U.S. Patent No. 10685715. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-2, 5-6 and 8 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively,
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1-2, 5-6 and 8 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
8. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1 and 3-9 of U.S. Patent No. 10157675. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1 and 3-9 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively,
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1 and 3-9 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
9. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, and 4-7 of U.S. Patent No. 9754672. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1, and 4-7 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, an operation time of the first operation; and resuming the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1, and 4-7 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
10. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1 and 3-10 of U.S. Patent No. 9437308. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1 and 3-10 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, operation being suspended at completion of one of the erase voltage apply steps; performing a first operation upon receipt of a first command, an operation time of the erase operation being longer than an operation time of the first operation; and resuming the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1 and 3-10 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and operation time of the erase operation being longer than an operation time of the first operation; and sends a resume command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
11. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 or 9-10 of U.S. Patent No. 9025390. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-2 or 9-10 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, upon receipt of a suspend command during performing one of the erase voltage apply steps, the erase operation being suspended at completion of one of the erase voltage apply steps; performing a first operation upon receipt of a first command, an operation time of the erase operation being longer than an operation time of the first operation; and resuming the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1-2 or 9-10 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and device to instruct the nonvolatile semiconductor memory device to perform a first operation, an operation time of the erase operation being longer than an operation time of the first operation; and sends a resume command to the nonvolatile semiconductor memory device to instruct the nonvolatile semiconductor memory device to resume the erase operation, the erase operation being resumed at start of one of the erase verify steps.
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
Claims 6-8 and 15-18 are obvious to Fig. 4 or 5 of Choi discloses a second terminal outputting a busy signal in Fig. 5 configured to output a ready/busy signal (a busy state, BUSY=HIGH; a ready state, BUSY=LOW).
12. Claims 1-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 8559236. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1 and 4 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and a second part of the memory cells, to gates of which the second word lines are connected, respectively, memory cells and the second part of the memory cells, the erase verify steps each performed after a corresponding one of the erase voltage apply steps;
Claims 9-18 of the examined application are anticipated and the same scope of invention by claims 1 and 4 of the reference such as a memory system comprising: a memory controller and a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including: a bit line; a plurality of first word lines; a plurality of second word lines; a source line; a memory block including a plurality of memory cells connected in series, the memory cells including: a first part of the memory cells, to gates of which the first word lines are connected, respectively; and
The claims 1-2 and 9 of examined application are obvious over the claim of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites ; a soft program step applied only to the second part of the memory cells; and a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step while in the reference claimed is silent. However, Choi discloses a soft program step (post program, block 3 of Fig. 3, col. 3, line 1-4) ; and a soft program verify step (block 3 of Fig. 3) performed after the soft program step. Column 4, lines 65-66 and Fig. 4 of Choi disclose wherein the control unit is further configured to: suspend and resuming the erase operation upon receipt of the suspend command during performing the soft program steps.
Claims 1 and 9 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells while in the reference claimed is silent. However, Fig. 2 of Nakamura discloses wherein the second word lines are dummy word lines (WLDD or WLDS), and the second memory cells are dummy memory cells (in WLDD OR WLDS).
Claims 4-5 and 13-14 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites holding status information into or output from a status register while in the reference claimed is silent. However, Fig. 26 and paragraphs 269 and 272 of Hamaguchi disclose wherein the control unit includes a status register (2060) configured to hold status information (par. 272), and configured to output the status information to an exterior (2999) of the device upon receipt of a status command.
Claims 6-8 and 15-18 are obvious to Fig. 4 or 5 of Choi discloses a second terminal outputting a busy signal in Fig. 5 configured to output a ready/busy signal (a busy state, BUSY=HIGH; a ready state, BUSY=LOW).
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14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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