DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 10 November 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Claims 1-19 are currently pending. Claims 1, 5-8, and 14 are amended as per Applicant’s amendment filed on 10 November 2025.
Response to Arguments
Applicant's arguments filed 10 November 2025 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The amended claims are address in the rejections below further in view of Buxton (US 20160259553 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Selinger (US 20110161554 A1) in view of Li (US 20120167100 A1) and Buxton (US 20160259553 A1).
Referring to claims 1, 8, and 14, taking claim 1 as exemplary, Selinger teaches
A flash memory controller for controlling a flash memory, wherein the flash memory controller comprises: ([Selinger abstract] controller for performing a sequence of commands, a controller receives a command from a host to perform a memory operation in a flash memory device) a first interface circuit coupled to the flash memory to transmit data and commands; ([Selinger 0016, Fig. 1] FIG. 1 is a system of an embodiment in which a controller 100 is in communication with a host 120 (having a host controller 121) through a first interface 125 and is in communication with one or more flash memory device(s) 130 through one or more second interface(s) 135. The number of second interface(s) 135 can match the number of flash memory device(s) 130, or the number of second interface(s) 135 can be greater than or less than the number of flash memory device(s) 130 (e.g., a single second interface 135 can support multiple flash memory device(s)).)) and a processor coupled to the first interface circuit to access the flash memory through the first interface circuit, ([Selinger 0016, 0019, Fig. 1] FIG. 1 is a system of an embodiment in which a controller 100 is in communication with a host 120 (having a host controller 121) through a first interface 125 and is in communication with one or more flash memory device(s) 130 through one or more second interface(s) 135. As shown in FIG. 1, the controller 100 also comprises a control module 140 for controlling the operation of the controller 100 and performing a memory operation based on a command (e.g., read, write, erase, etc.) and an address received from the host 120. As used herein, a "module" can include hardware, software, firmware, or any combination thereof. Examples of forms that a "module" can take include, but are not limited to, one or more of a microprocessor or processor and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example.) wherein the processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory; ([Selinger 0051-0052, Fig. 3] a controller between the host and one or more NAND flash memory devices can be used to group a sequence of commands together and process them together, even though the commands are received from the host one-command-at-a-time. This allows the controller to perform multi-plane, pipelined, and queued commands. the host 320 is aware of the logical operations it wants performed and uses a standard NAND interface to issue standard commands to a "smarter" controller 300. The controller 300 can then, when appropriate, group a sequence of commands together and process them as a group, even though the commands are received from the host 320 one-command-at-a-time.) and wherein the first command sequence comprises a first command and a second command, ([Selinger 0054-0057] When the command is received, the controller 300 analyzes the CB to determine whether it indicates that the command is a stand-alone command or is part of a sequence of commands (act 420). If the CB indicates that the command is a stand-alone command (e.g., CB=0), the controller 300 performs the command (act 430). However, if the CB indicates that the command is part of a sequence of commands (e.g., CB=1), the controller 320 performs the command as part of the sequence of commands (act 440). That is, the controller 300 would translate the command as a super-command set where it can be a representation of, for example, (1) a command in a group of commands targeted to all planes, (2) a command in a group of commands that should be treated together as an atomic command sequence, (3) or a command that is part of a sequential group of commands with incremental addresses. Thus, in this example, a string of commands with CB=1 would be treated by the controller 300 as part of a sequence of commands to be processed together, with the last command in the group having CB=0. providing a controller that can perform a sequence of commands can help maximize performance of a flash die by executing two or more overlapped operations (e.g., reads, programs (writes), or erases), frequently to different planes) the first command is configured to instruct the flash memory to receive address information, and in response to the transmission of the second command, the flash memory executes an erase operation corresponding to the address information, ([Selinger 0057, 0058, 0062, 0064, Fig. 7] providing a controller that can perform a sequence of commands can help maximize performance of a flash die by executing two or more overlapped operations (e.g., reads, programs (writes), or erases), frequently to different planes. There are several different operation types that can be used in these embodiments, and they can generally fall into two categories: (1) commands that transfer any data before status or (2) commands that transfer data after status. A program operation is an example of the first category, while reads are examples of the second. An erase command does not perform a data transfer and can be considered another example of the first category. For operations in the first category, the controller 300 can return a status after each program part. Consider, for example, a single program command sequence can consist of (1) command, (2) address, (3) data transfer, and (4) device busy until status returned. The host 320 will discover the command PCMD[A] is ready via the ready/busy signal or by polling the status or extended status register and initiate data transfer from the controller 300. FIG. 7 is a timing diagram of a multi-plane block erase operation of an embodiment. In operation, the host 320 would issue a Block Erase command ((60) BAddr (D0))--referred to as PCMD[A]--with CB set=1 to start a multi-plane block erase. The controller 300 receives the command and detects the CB bit in the address field. The controller 300 can have pre-defined logic to determine if the command is the last command of the multi-plane operation. If the command is not the last command, the controller 300 can mark the LUN status to ready. When the host 320 discovers that the LUN is ready, it is able to issue the next block erase command ((60) BAddr (D0))--referred as PCMD[B]--with CB set to the next plane.) of an erase command, a write command, or a read command ([Selinger 0019, 0057-0058, 0062] performing a memory operation based on a command (e.g., read, write, erase, etc.)).
Selinger does not explicitly disclose and when an array ready status bit is in a non-ready status, the second command sequence is transmitted to the flash memory, wherein the second command sequence comprises at least one. Selinger does disclose "Flash memory device(s)" refer to device(s) containing a plurality of flash memory cells and any necessary control circuitry for storing data within the flash memory cells, such as passive element arrays, ready/busy signal, device busy until status returned, and if the command is not the last command, the controller 300 can mark the LUN status to ready ([Selinger 0018, 0058, 0062, 0064, Fig. 7]). Selinger additionally discloses performing a memory operation based on a command (e.g., read, write, erase, etc.) and sequence of commands and issuing next commands ([Selinger 0019, 0057-0058, 0062]).
Li teaches and when an array ready status bit is in a non-ready status, the second command sequence is transmitted to the flash memory ([Li 0050, 0093, 0095-0103, Fig. 6A, 6B] communication path can have a ready or busy status (identified by the signal ExternalBusyn discussed further below) which is set by the control circuitry to indicate whether it is ready or busy. In one possible option, the external controller can access a ready/busy pin to determine the ready/busy status, via an auxiliary channel. In another possible option, the external controller accesses the ready/busy status via the same communication path over which it communicates commands and data. When the control circuitry is ready, the external controller knows that it is able to send commands and data to the control circuitry via the one or more communication paths, and the control circuitry is waiting to receive such commands, address and data. When the control circuitry is busy, the external controller waits to send most commands and data to the control circuitry. Commands for suspending and resuming tasks can be provided from the external controller to the control circuitry when the status is ready or busy, but may not be acted on by the control circuitry immediately when the status is busy depending on the stage of flash operation. FIG. 6A depicts an overview of a process in which an external controller communicates with control circuitry on a memory die. In an example process, at step 600, the external controller issues commands, including manual suspend and resume commands, checks a task status and a ready/busy status of the control circuitry and maintains a records of in-progress tasks. At step 602, the control circuitry responds to commands from the external controller, suspends and resumes tasks, and sets a task status, including a suspend status and a ready/busy status. At step 614, in response to sensing the ready status, the external controller issues a second command to perform a second task. The external controller can constantly monitor the communication channel to determine when it transitions from busy to ready. At step 615, the external controller updates a record to indicate that the second task has been issued (see FIG. 6C). FIG. 6C depicts examples of a record which identifies in-progress tasks as discussed at step 614 of FIG. 6B. The external controller can maintain a record of one or more tasks which have been issued to the control circuitry. In one approach, a task is added to the record when the task is issued to the control circuitry and removed from the record when the external controller determines from status data that the task has been successfully completed or otherwise terminated (e.g., aborted). For example, assume that initially only task1 has been issued, as depicted by the record 630.).
Selinger and Li are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Selinger and Li before him or her to modify the memory device ready/busy signal of Selinger to include the ready status operation of Li, thereafter the memory device ready/busy signal is connected to ready status operation. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to use the ready/busy signal for sequences operations and commands as suggested by Li. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Selinger with Li to obtain the invention as specified in the instant application claims.
Selinger in view of Li does not explicitly disclose wherein the second command sequence comprises at least one. Selinger discloses performing a memory operation based on a command (e.g., read, write, erase, etc.) and sequence of commands and issuing next commands ([Selinger 0019, 0057-0058, 0062]).
Buxton teaches wherein the second command sequence comprises at least one ([Buxton 0034, Fig. 4b] In FIG. 4b, a second command 440 is shown arriving while the first command is processing. Since the polled Ready/Busy state 420 is Busy, the command is queued 440.).
Selinger, Li, and Buxton are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Selinger, Li, and Buxton before him or her to modify the memory device ready/busy signal command handling of Selinger and Li to include the second command queuing of Buxton, thereafter the memory device ready/busy signal command handling is connected to second command queueing. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to use the ready/busy signal for sequences operations and commands as suggested by Li and Buxton. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Selinger and Li with Buxton to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to the non-exemplary limitations of claim 14, Li additionally teaches setting an array ready status bit to a non-ready status in response to the receiving of a second command of the first command sequence ([Li 0050, 0093, 0095-0103, Fig. 6A, 6B] communication path can have a ready or busy status (identified by the signal ExternalBusyn discussed further below) which is set by the control circuitry to indicate whether it is ready or busy. In one possible option, the external controller can access a ready/busy pin to determine the ready/busy status, via an auxiliary channel. In another possible option, the external controller accesses the ready/busy status via the same communication path over which it communicates commands and data. When the control circuitry is ready, the external controller knows that it is able to send commands and data to the control circuitry via the one or more communication paths, and the control circuitry is waiting to receive such commands, address and data. When the control circuitry is busy, the external controller waits to send most commands and data to the control circuitry. Commands for suspending and resuming tasks can be provided from the external controller to the control circuitry when the status is ready or busy, but may not be acted on by the control circuitry immediately when the status is busy depending on the stage of flash operation. FIG. 6A depicts an overview of a process in which an external controller communicates with control circuitry on a memory die. In an example process, at step 600, the external controller issues commands, including manual suspend and resume commands, checks a task status and a ready/busy status of the control circuitry and maintains a records of in-progress tasks. At step 602, the control circuitry responds to commands from the external controller, suspends and resumes tasks, and sets a task status, including a suspend status and a ready/busy status. At step 614, in response to sensing the ready status, the external controller issues a second command to perform a second task. The external controller can constantly monitor the communication channel to determine when it transitions from busy to ready. At step 615, the external controller updates a record to indicate that the second task has been issued (see FIG. 6C). FIG. 6C depicts examples of a record which identifies in-progress tasks as discussed at step 614 of FIG. 6B. The external controller can maintain a record of one or more tasks which have been issued to the control circuitry. In one approach, a task is added to the record when the task is issued to the control circuitry and removed from the record when the external controller determines from status data that the task has been successfully completed or otherwise terminated (e.g., aborted). For example, assume that initially only task1 has been issued, as depicted by the record 630.).
Referring to claims 2, 9, and 15, taking claim 2 as exemplary, Selinger in view of Li and Buxton teaches
The flash memory controller of claim 1, wherein the flash memory is in the non-ready status when the array ready status bit of the flash memory is set to 0, and the flash memory is in a ready status when the array ready status bit of the flash memory is set to 1 ([Li 0050-0051, 0098-0103,Fig. 6B] The communication path can have a ready or busy status (identified by the signal ExternalBusyn discussed further below) which is set by the control circuitry to indicate whether it is ready or busy. In one possible option, the external controller can access a ready/busy pin to determine the ready/busy status, via an auxiliary channel. In another possible option, the external controller accesses the ready/busy status via the same communication path over which it communicates commands and data. The external controller can thus communicate with the control circuitry at any time, even when the busy status is set for the communication path. Sets ready status including at steps 613 and 616).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claim 3, Selinger in view of Li and Buxton teaches
The flash memory controller of claim 1, wherein in response to the transmission of the second command, a ready status bit of the flash memory and the array ready status bit are set to 0, and after a first busy period, the ready status bit is set to 1 and the array ready status bit is set to 0 ([Li 0050-0051, 0098-0103,Fig. 6B] The communication path can have a ready or busy status (identified by the signal ExternalBusyn discussed further below) which is set by the control circuitry to indicate whether it is ready or busy. In one possible option, the external controller can access a ready/busy pin to determine the ready/busy status, via an auxiliary channel. In another possible option, the external controller accesses the ready/busy status via the same communication path over which it communicates commands and data. The external controller can thus communicate with the control circuitry at any time, even when the busy status is set for the communication path. Sets ready status including at steps 613 and 616 and in response to sensing the ready status at steps 614 and 617.).
Referring to claims 4, 10, and 16, taking claim 4 as exemplary, Selinger in view of Li and Buxton teaches
The flash memory controller according to claim 1, wherein the processor controls the first interface circuit to transmit a set feature command sequence to the flash memory before transmitting the first command sequence, the set feature command sequence is configured to enable the flash memory controller to transmit the second command sequence to the flash memory when the array ready status bit is in the non-ready status ([Selinger 0054-0056, Fig. 4] Turning now to the flowchart 400 in FIG. 4, the controller 300 receives a command from the host 320 to perform a memory operation in the flash memory device 330 (act 410). In this embodiment, the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The at least one bit can be any number of bits and, in one embodiment, is a single bit that is one of a plurality of reserved address bits in the command. In this particular example, the at least one bit is the most significant address bit and will be referred to herein as a "continuation bit" or "chaining bit" (or "CB"). When the command is received, the controller 300 analyzes the CB to determine whether it indicates that the command is a stand-alone command or is part of a sequence of commands (act 420). If the CB indicates that the command is a stand-alone command (e.g., CB=0), the controller 300 performs the command (act 430). However, if the CB indicates that the command is part of a sequence of commands (e.g., CB=1), the controller 320 performs the command as part of the sequence of commands (act 440). That is, the controller 300 would translate the command as a super-command set where it can be a representation of, for example, (1) a command in a group of commands targeted to all planes, (2) a command in a group of commands that should be treated together as an atomic command sequence, (3) or a command that is part of a sequential group of commands with incremental addresses. Thus, in this example, a string of commands with CB=1 would be treated by the controller 300 as part of a sequence of commands to be processed together, with the last command in the group having CB=0.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 5, 11, and 17, taking claim 5 as exemplary, Selinger in view of Li and Buxton teaches
The flash controller memory of claim 1, wherein the second command sequence comprises the same commands as the first command sequence, and during a timing interval of the flash memory executing operations corresponding to the first command sequence and the second command sequence, the array ready status bit remains in the non-ready status ([Selinger 0056-0057, 0082-0084, Fig. 8C, 8D] so the ONFI HIM is required to simultaneously handle multiple (e.g., eight) read and write requests. the host 320 can generate multiple standard IO commands, each with the CB set, to a NAND device driver. The NAND device driver would then interact with NAND bus master hardware to execute each CB command as a normal command. Accordingly, these embodiments can be used to create overlapped writes (or other commands). when operation is done, a ready indicator is stored in the status register).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 6, 12, and 18, taking claim 6 as exemplary, Selinger in view of Li and Buxton teaches
The flash controller memory of claim 1, wherein the second command sequence is configured to instruct the flash memory to execute a read operation, and during a timing interval of the flash memory executing operations corresponding to the first command sequence and the second command sequence, the array ready status bit remains in the non-ready status ([Selinger 0083-0084, Fig. 8C] FIGS. 8C and 8D illustrate the logical operations of an ONFI HIM for read and write operations, respectively. Turning first to FIG. 8C, the ONFI HIM 3480 of this embodiment receives a read command from a host controller through an ONFI bus 3490. The ONFI HIM 3480 can operate in an asynch or a source synch mode and communicates the read command to a command FIFO 3540 via signal multiplexors 3500, 3530. (The ONFI HIM 3480 can be used in an async mode and source sync mode using the Async and ONFI source sync components 3510, 3520, respectively.) The ONFI HIM 3480 also stores the address received from the host controller in a logical unit number ("LUN") address FIFO 3550. (The NAND controller in this embodiment supports multiple logical units, which are treated as independent entities that are addressable by LUN addresses.) The command and address are read from the FIFOs 3540, 3550 into a command and data controller 3560, which synchronizes these items. The command and data controller 3560 then sends an interrupt to the system register controller 3570, which generates an interrupt to the ARC600 microcontroller. The ARC600 microcontroller then reads the LUN address from the register in the system register controller 3570, and the process of reading data from the flash memory device(s) is as described above. When all the read data is written to the DRAM, the ARC600 microprocessor program the status register in the system register controller 3570 to inform the ONFI HIM 3480 that the data is ready to be read. The ONFI HIM 3480 then reads the data through the HDMA 3580 using the read request control unit 3585. The read data is stored in the read data FIFO 3590, which is partitioned for each LUN 3595. Once that is done, a ready indicator is stored in the status register, and the data is streamed to the host controller.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 7, 13, and 19, taking claim 7 as exemplary, Selinger in view of Li and Buxton teaches
The flash controller memory of claim 1, wherein the second command sequence is configured to instruct the flash memory to execute a write operation, and during a timing interval of the flash memory executing operations corresponding to the first command sequence and the second command sequence, the array ready status bit remains in the non-ready status ([Selinger 0083-0084, Fig. 8D] Turning now to FIG. 8D, in a write operation, a write command is received from a host controller through an ONFI 3410 bus. The ONFI HIM 3400 communicates the write command to a command FIFO 3460 via signal multiplexors 3420, 3450. (The ONFI HIM 3400 can be used in an async mode and source sync mode using the Async and ONFI source sync components 3430, 3440, respectively.) The ONFI HIM 3400 also stores the address received from the host controller in a logical unit number ("LUN") address FIFO 3470. The data received from the host controller is stored in a write data FIFO 3520. The command and address are read from the FIFOs 3460, 3470 into a command and data controller 3480, which synchronizes these items. The command and data controller 3480 then sends an interrupt to the system register controller 3490, which generates an interrupt to the ARC600 microcontroller. The ARC600 microcontroller then reads the LUN address from the register in the system register controller 3490, and the process of setting-up the controller from a write operation is as described above. The HDMA 3530 has an AHB port 3540 in communication with the AHB bus 3550 and sends the data to the DRAM. The CRC module 3545 checks for transmission errors in the data. Once the data has been stored in the flash memory device(s) 330 and the flash memory device(s) 330 indicate ready and the status of program operation is successful or fail, a ready indicator is stored in the status register in the system register controller 3490, indicating that the ONFI HIM 3400 is ready for another command from the host controller.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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