DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The objections to the specification have been withdrawn in view of applicant’s amendments filed on 06/11/2026
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7-9, 11, 13-15, 17-19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 20230343299) in view of Koselj et al. (U.S. Pub. No. 20050041039).
Regarding claim 1, Lee discloses an electronic device (Lee: paragraph 8, line(s) 1-2 "Various embodiments of the disclosure may provide an electronic device"): image processing circuitry (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") configured to generate a frame of image data (Lee: paragraph 59, line(s) 1-4 "In an embodiment, the DDI 230 may generate a synchronization signal. The synchronization signal may be a signal for controlling a time point at which a data voltage is supplied to the display panel 210"); configured to: receive an operating condition from an application processor (para 49, “For example, the DDI 230 may receive image information including image data or an image control signal corresponding to a command for controlling the image data from another component of an electronic device 101 through the interface module 231. For example, according to an embodiment, the image information may be received from the processor 120 (e.g., the main processor 121) (e.g., an application processor) or the auxiliary processor 123 (e.g., a graphic processing display) that operates independently of the function of the main processor 121.”; also, para 81, “In an embodiment, a processor (e.g., the processor 120 in FIG. 3) may set the operating frequency of a DDI (e.g., the DDI 230 in FIG. 3) based on the length of the waiting period.”); generate a display parameter based on the operating condition; and configure the image processing circuitry (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") based on the display parameter (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210"; also, paragraph 49, line(s) 26-38 "The mapping module 237 may generate a voltage value or a current value corresponding to the image data that is pre-processed or post-processed through the image processing module 235. According to an embodiment, for example, the voltage value or the current value may be generated based at least partly on attributes (e.g., an array of pixels (RGB stripe or pentile structure) or a size of each of sub-pixels) of the display panel 210. For example, at least some pixels of the display panel 210 may be driven based at least partly on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is capable of being displayed through the display panel 210"). Lee does not disclose the acceleration sub-system and by writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry.
However, in a similar field of endeavor, Koselj discloses an acceleration sub-system (Koselj: FIG. 20, label 1; also, paragraph 203, line(s) 6-8, "a control circuit for control of the gate driver, LCD driver circuit, interface circuit and graphics accelerator"), and by writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry (para 223, “A set of control/status registers is used to control the operation of the circuit. Host CPU writes values to control registers (via the interface circuit) to assign mode of operation and instruct circuitry what to do with consequent data coming from host CPU.”; also, para 211, “For example, data transfer can be writing to a control register (control logic) to instruct the operation of the circuitry or reading a control/status register to verify the status of the circuitry or status of operation performing (finished or not finished).”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee's invention of an electronic device with image processing circuitry configured to generate a frame of image data, receiving an operating condition from an application processor, generating a display parameter based on the operating condition, and configuring the image processing circuitry based on the display parameter with the features of Koselj's invention of an acceleration sub-system that configures circuitry by writing values to at least one register of the circuitry. A person of ordinary skill would have made this combination because Koselj teaches that a hardware graphics accelerator relieves the host processor of display processing and that writing values to control registers through the interface circuit assigns the mode of operation of the display driver circuitry, yielding the predictable result of an electronic device in which the display parameter is applied to the image processing circuitry by a dedicated acceleration sub-system through a register write.
Regarding claim 2, Lee as modified by Koselj, discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system configures the image processing circuitry prior to the image processing circuitry generating the frame of image data (Lee: paragraph 59, line(s) 1-4 "In an embodiment, the DDI 230 may generate a synchronization signal. The synchronization signal may be a signal for controlling a time point at which a data voltage is supplied to the display panel 210"; also, paragraph 49, line(s) 26-38 "The mapping module 237 may generate a voltage value or a current value corresponding to the image data that is pre-processed or post-processed through the image processing module 235. According to an embodiment, for example, the voltage value or the current value may be generated based at least partly on attributes (e.g., an array of pixels (RGB stripe or pentile structure) or a size of each of sub-pixels) of the display panel 210. For example, at least some pixels of the display panel 210 may be driven based at least partly on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is capable of being displayed through the display panel 210"; also, paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210").
Regarding claim 3, Lee as modified by Koselj discloses the electronic device of claim 1,wherein the operating condition comprises a display brightness value, a temperature value, a frame duration, or an ambient condition (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210").
Regarding claim 5, Lee as modified by Koselj, discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system comprises a processor (Lee: paragraph 18, line(s) 1 "FIG. 3 is a block diagram illustrating a processor") configured to perform an operation using the operating condition to generate the display parameter (Lee: paragraph 32, line(s) 1-3 "The input module 150 may receive instructions or data to be used for the component (e.g., the processor 120) of electronic device 101,"; also, paragraph 49, line 22-28 "The mapping module 237 may generate a voltage value or a current value corresponding to the image data that is pre-processed or post-processed through the image processing module 235. According to an embodiment, for example, the voltage value or the current value may be generated based at least partly on attributes (e.g., an array of pixels (RGB stripe or pentile structure) or a size of each of sub-pixels) of the display panel 210. For example, at least some pixels of the display panel 210 may be driven based at least partly on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is capable of being displayed through the display panel 210.").
Regarding claim 7, Lee as modified by Koselj discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system comprises a hardware accelerator (koseli: FIG. 20, label 1, also, paragraph 87, line(s) 1-3, "FIG. 20 is a schematic representation of a source driver IC incorporating a graphics engine and its links to CPU, the display area and a gate driver IC"; also, paragraph 6, line(s) 4-6, "hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard")configured to generate the display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2). The graphics processing unit 310 may provide the image data to an application processor (AP) included in the processor 120") by: converting the operating condition (Lee: paragraph 32, line(s) 1-3 "The input module 150 may receive instructions or data to be used for the component (e.g., the processor 120) of electronic device 101,") from a first format or a first precision to a second format or a second precision, wherein the second format is different from the first format, and wherein the second precision different from the first precision (Lee: paragraph 56, line(s) 6-10 "The operating frequency and the length of one frame may have an inversely proportional relationship. For example, when the DDI 230 operates at the operating frequency of about 60 Hz, the length of one frame may be about 16.67 ms(millisecond)"); and generating the display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2) in the second format or the second precision.
Regarding claim 8, Lee as modified by Koselj discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system comprises a hardware accelerator (koseli: FIG. 20, label 1, also, paragraph 87, line(s) 1-3, "FIG. 20 is a schematic representation of a source driver IC incorporating a graphics engine and its links to CPU, the display area and a gate driver IC"; also, paragraph 6, line(s) 4-6, "hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard") configured to generate the display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2). The graphics processing unit 310 may provide the image data to an application processor (AP) included in the processor 120") by performing a mathematical function using the operating condition (Lee: paragraph 82, line(s) 1-9 "the processor 120 may be configured to determine pixel characteristic values included in the image data 620 based on the operating frequency. The pixel characteristic values may be values set for pixels included in a display panel (e.g., the display panel 210 in FIG. 2) to represent an image. For example, the pixel characteristic values may include, for example, a gamma characteristic value, a color ratio value, or an emission timing value.").
Regarding claim 9, Lee as modified by Koselj by discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system comprises a local memory configured to store one or more operating conditions (paragraph 28, line(s) 5-12 "According to an embodiment, as at least part of data processing or calculation, the processor 120 may store instructions or data received from other components (e.g., the sensor module 176 or the communication module 190) into a volatile memory 132, may process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134"; also, paragraph 49, line(s) 22-25 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data").
Regarding claim 11, Lee discloses a method (paragraph 2, line(s) 1-2 "The disclosure relates to an electronic device and a control method thereof.") comprising: an operating condition (paragraph 32, line(s) 1-3 "The input module 150 may receive instructions or data to be used for the component (e.g., the processor 120) of electronic device 101,"); generating a display parameter (paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210") based on the operating condition (paragraph 32, line(s) 1-3 "The input module 150 may receive instructions or data to be used for the component (e.g., the processor 120) of electronic device 101,"); and adjusting, via the image processing circuitry (paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") based on the display parameter (paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210"; also, paragraph 49, line(s) 26-38 "The mapping module 237 may generate a voltage value or a current value corresponding to the image data that is pre-processed or post-processed through the image processing module 235. According to an embodiment, for example, the voltage value or the current value may be generated based at least partly on attributes (e.g., an array of pixels (RGB stripe or pentile structure) or a size of each of sub-pixels) of the display panel 210. For example, at least some pixels of the display panel 210 may be driven based at least partly on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is capable of being displayed through the display panel 210"). Lee does not disclose the use of an accelerator sub-system and wherein adjusting the image processing circuitry comprises writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuity.
However, in a similar field of endeavor, Koselj discloses the use of an accelerator sub-system (Koselj: FIG. 20, label 1; also, paragraph 203, line(s) 6-8, "a control circuit for control of the gate driver, LCD driver circuit, interface circuit and graphics accelerator"; also, para 203, “The source IC, which is both the driver and controller IC, has a control circuit for control of the gate driver, LCD driver circuit, interface circuit and graphics accelerator.”; also, para 6, “In the rather different technical area of personal computers and computer networks, the problem of displaying sophisticated graphics at an acceptable speed is often solved by a hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard.”) and wherein adjusting the image processing circuitry comprises writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuity (para 223, “A set of control/status registers is used to control the operation of the circuit. Host CPU writes values to control registers (via the interface circuit) to assign mode of operation and instruct circuitry what to do with consequent data coming from host CPU.”; also, para 211, “For example, data transfer can be writing to a control register (control logic) to instruct the operation of the circuitry or reading a control/status register to verify the status of the circuitry or status of operation performing (finished or not finished).”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee's invention of a method of receiving an operating condition, generating a display parameter based on the operating condition, and adjusting image processing circuitry based on the display parameter with the features of Koselj's invention of an accelerator sub-system that adjusts circuitry by writing values to at least one register of the circuitry. A person of ordinary skill would have made this combination because Koselj teaches that a hardware graphics accelerator relieves the host processor of display processing and that writing values to control registers through the interface circuit assigns the mode of operation of the display driver circuitry, yielding the predictable result of a method in which the display parameter is applied to the image processing circuitry by a dedicated accelerator sub-system through a register write.
Regarding claim 13, Lee as modified by Koselj discloses the method of claim 11 and the accelerator sub-system, wherein generating, via the accelerator sub-system, the display parameter comprises converting the operating condition from a first precision to a second precision (Lee: paragraph 56, line(s) 6-10 "The operating frequency and the length of one frame may have an inversely proportional relationship. For example, when the DDI 230 operates at the operating frequency of about 60 Hz, the length of one frame may be about 16.67 ms(millisecond)").
Regarding claim 14, Lee as modified by Koselj discloses the method of claim 11 and the accelerator sub-system, wherein generating, via the accelerator sub-system, the display parameter comprises converting the operating condition from a first format to a second format (Lee: paragraph 56, line(s) 6-10 "The operating frequency and the length of one frame may have an inversely proportional relationship. For example, when the DDI 230 operates at the operating frequency of about 60 Hz, the length of one frame may be about 16.67 ms(millisecond)").
Regarding claim 15, Lee as modified by Koselj discloses the method of claim 11 and the accelerator sub-system, wherein generating, via the accelerator sub-system, the display parameter comprises performing a mathematical function using the operating condition (Lee: paragraph 82, line(s) 1-9 "the processor 120 may be configured to determine pixel characteristic values included in the image data 620 based on the operating frequency. The pixel characteristic values may be values set for pixels included in a display panel (e.g., the display panel 210 in FIG. 2) to represent an image. For example, the pixel characteristic values may include, for example, a gamma characteristic value, a color ratio value, or an emission timing value.").
Regarding claim 17, Lee discloses a system (Lee: paragraph 31, line(s) 1-3 "The program 140 may be stored as software in the memory 130 and may include, for example, an operating system 142, a middleware 144, or an application 146") comprising: image processing circuitry (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") comprising a plurality of display parameters (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210") and configured to generate a frame of image data (Lee: paragraph 59, line(s) 1-4 "In an embodiment, the DDI 230 may generate a synchronization signal. The synchronization signal may be a signal for controlling a time point at which a data voltage is supplied to the display panel 210"); and an accelerator sub-system configured to adjust a display parameter (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210") of the plurality of display parameters (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210") of the image processing circuitry prior to generation of the frame of image data (Lee: paragraph 59, line(s) 1-4 "In an embodiment, the DDI 230 may generate a synchronization signal. The synchronization signal may be a signal for controlling a time point at which a data voltage is supplied to the display panel 210"; also, paragraph 49, line(s) 26-38 "The mapping module 237 may generate a voltage value or a current value corresponding to the image data that is pre-processed or post-processed through the image processing module 235. According to an embodiment, for example, the voltage value or the current value may be generated based at least partly on attributes (e.g., an array of pixels (RGB stripe or pentile structure) or a size of each of sub-pixels) of the display panel 210. For example, at least some pixels of the display panel 210 may be driven based at least partly on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is capable of being displayed through the display panel 210"; also, paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210"), wherein the accelerator sub-system comprises: a processor configured to: retrieve an operating condition (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") from local memory (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"); and perform an operation using the operating condition (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor."); configured to: receive the operating condition (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.") from the processor; generate an updated display parameter by performing an additional operation using the operating condition (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor."). Lee does not disclose the use of an accelerator sub-system, a hardware accelerator, and adjust the display parameter by writing the updated display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry.
However, in a similar field of endeavor, Koselj discloses an acceleration sub-system, a hardware accelerator (Koselj: FIG. 20, label 1; also, paragraph 203, line(s) 6-8, "a control circuit for control of the gate driver, LCD driver circuit, interface circuit and graphics accelerator"; also, FIG. 20 is a schematic representation of a source driver IC incorporating a graphics engine and its links to CPU, the display area and a gate driver IC"; also, paragraph 6, line(s) 4-6, "hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard"; also, para 203, “The source IC, which is both the driver and controller IC, has a control circuit for control of the gate driver, LCD driver circuit, interface circuit and graphics accelerator.”; also, para 6, “In the rather different technical area of personal computers and computer networks, the problem of displaying sophisticated graphics at an acceptable speed is often solved by a hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard.”), and adjust the display parameter by writing the updated display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry (para 223, “A set of control/status registers is used to control the operation of the circuit. Host CPU writes values to control registers (via the interface circuit) to assign mode of operation and instruct circuitry what to do with consequent data coming from host CPU.”; also, para 211, “For example, data transfer can be writing to a control register (control logic) to instruct the operation of the circuitry or reading a control/status register to verify the status of the circuitry or status of operation performing (finished or not finished).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee's invention of a system with image processing circuitry comprising a plurality of display parameters and configured to generate a frame of image data, a processor retrieving an operating condition from local memory and performing an operation using the operating condition, and generating an updated display parameter using the operating condition with the features of Koselj's invention of an accelerator sub-system and a hardware accelerator that adjusts circuitry by writing values to at least one register of the circuitry. A person of ordinary skill would have made this combination because Koselj teaches that a hardware graphics accelerator relieves the host processor of display processing and that writing values to control registers through the interface circuit assigns the mode of operation of the display driver circuitry, yielding the predictable result of a system in which the updated display parameter is applied to the image processing circuitry by a dedicated hardware accelerator through a register write.
Regarding claim 18, Lee as modified by Koselj discloses the system of claim 17, wherein generating the updated display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2) comprises converting the operating condition from a first precision and/or format to a second precision and/or format (Lee: paragraph 56, line(s) 6-10 "The operating frequency and the length of one frame may have an inversely proportional relationship. For example, when the DDI 230 operates at the operating frequency of about 60 Hz, the length of one frame may be about 16.67 ms(millisecond)").
Regarding claim 19, Lee as modified by Koselj discloses the system of claim 17, generating the updated display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2) comprises performing a mathematical function (Lee: paragraph 82, line(s) 1-9 "the processor 120 may be configured to determine pixel characteristic values included in the image data 620 based on the operating frequency. The pixel characteristic values may be values set for pixels included in a display panel (e.g., the display panel 210 in FIG. 2) to represent an image. For example, the pixel characteristic values may include, for example, a gamma characteristic value, a color ratio value, or an emission timing value.") using the operating condition (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor.").
Regarding claim 21, Lee in view of Koselj discloses the electronic device of claim 1,
However, in a similar field of endeavor, Koselj discloses wherein the acceleration sub-system is separate from the image processing circuitry (para 56, “One graphics engine may be provided per driver IC. However, where the graphics engine is not provided on the driver IC it may service a plurality of ICs in the display module, such as a plurality of source ICs used to drive a slightly larger display. The graphics engine in this case may be provided its own separate IC, or it may be embedded in a master source driver that controls the remaining source drivers.”; also, para 6, “In the rather different technical area of personal computers and computer networks, the problem of displaying sophisticated graphics at an acceptable speed is often solved by a hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee's invention of an electronic device with image processing circuitry configured to generate a frame of image data, receiving an operating condition from an application processor, generating a display parameter based on the operating condition, and configuring the image processing circuitry based on the display parameter with the features of Koselj's invention of an acceleration sub-system provided as its own separate integrated circuit apart from the driver circuitry it serves. A person of ordinary skill would have made this combination because Koselj teaches that a graphics engine provided on its own separate integrated circuit can service a plurality of driver integrated circuits in the display module, yielding the predictable result of an acceleration sub-system that is separate from the image processing circuitry it configures.
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 2023/0343299) in view of Koselj et al. (U.S. Pub. No. 2005/0041039). as applied to claim 1 and 11 above, and further in view of Mombers (U.S. Pub. No. 2024/0036823).
Regarding claim 6, Lee as modified by Koselj discloses the electronic device of claim 1 and the acceleration sub-system, wherein the acceleration sub-system comprises a hardware accelerator (koseli: FIG. 20, label 1, also, paragraph 87, line(s) 1-3, "FIG. 20 is a schematic representation of a source driver IC incorporating a graphics engine and its links to CPU, the display area and a gate driver IC"; also, paragraph 6, line(s) 4-6, "hardware graphics engine (also known as a graphics accelerator) on an extra card that is housed in the processor box or as an embedded unit on the motherboard") configured to generate the display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2). The graphics processing unit 310 may provide the image data to an application processor (AP) included in the processor 120"). Lee as modified by Koselj does not disclose the process of retrieving at least two look-up tables and generating a combined look-up table by interpolating between each look-up table of the at least two look-up tables.
However, in a similar field of endeavor, Mombers discloses the process of retrieving at least two look-up tables and generating a combined look-up table by interpolating between each look-up table of the at least two look-up tables (Mombers: paragraph 13, line(s) 8-19 "A lookup table may include an array of entries stored in memory where each entry includes one or more items of data. The array of entries may be indexed so that each entry has an associated index value that may be used to locate the entry within the array of entries and in memory to retrieve the one or more data items in the entry. According to aspects of the subject technology, the input mantissa from an input floating-point element may be used to index into lookup tables and the values retrieved from the lookup tables may be used to interpolate the output mantissa for the output floating-point element."; also, paragraph 24, line(s) 6-11 "The generated output mantissa is an estimate that is generated using the input mantissa to index lookup tables stored in memory 240, retrieve samples for the function and other information from the lookup tables, and interpolate the output mantissa using the retrieved samples and other information").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have additionally modify Lees invention as modified by Koselj of the electronic device of claim 1, the acceleration sub-system, the hardware accelerator, generate the display parameter with the features of Mombers invention of retrieving at least two look-up tables based on the operating condition; and generating a combined look-up table by interpolating between each look-up table of the at least two look-up tables. As demonstrated by Mombers, one could further disclose the process of calculating the various data from a series of lookup tables based on the operating condition and generated an interpolated value from a series of lookup tables.
Regarding claim 12, Lee as modified by Koselj discloses the method of claim 11 and the accelerator sub-system, wherein generating, via the accelerator sub-system, the display parameter (Lee: paragraph 49, line(s) 22-26 "the image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least part of the image data based at least on characteristics of the image data or the display panel 210") comprises: retrieving two or more look-up tables from system memory (Lee: paragraph 49, line(s) 1-7 " FIG. 2 is a block diagram 200 of the display module 160, according to various embodiments. Referring to FIG. 2, the display module 160 may include a display panel 210 and a display driver IC (DDI) 230 for controlling the display panel 210. The DDI 230 may include an interface module 231, a memory 233 (e.g., a buffer memory), an image processing module 235, or a mapping module 237.") based on the operating condition (Lee: paragraph 32, line(s) 1-3 "The input module 150 may receive instructions or data to be used for the component (e.g., the processor 120) of electronic device 101,"); and generating the display parameter (Lee: paragraph 28, line(s) 10-19 "process instructions or data stored in the volatile memory 132, and may store the result data in a nonvolatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor"; also, paragraph 53 ,line(s) 2-7 "The graphics processing unit 310 may generate image data. The image data may define a screen output on a display panel (e.g., the display panel 210 in FIG. 2). The graphics processing unit 310 may provide the image data to an application processor (AP) included in the processor 120") by interpolating between the two or more look-up tables. Lee does not disclose the process of retrieving two or more look-up tables from system memory and interpolating between the two or more look-up tables.
However, in a similar field of endeavor, Mombers discloses the process of retrieving two or more look-up tables from system memory and interpolating between the two or more look-up tables (Momnbers: paragraph 13, line(s) 8-19 "A lookup table may include an array of entries stored in memory where each entry includes one or more items of data. The array of entries may be indexed so that each entry has an associated index value that may be used to locate the entry within the array of entries and in memory to retrieve the one or more data items in the entry. According to aspects of the subject technology, the input mantissa from an input floating-point element may be used to index into lookup tables and the values retrieved from the lookup tables may be used to interpolate the output mantissa for the output floating-point element."; also, paragraph 24, line(s) 6-11 "The generated output mantissa is an estimate that is generated using the input mantissa to index lookup tables stored in memory 240, retrieve samples for the function and other information from the lookup tables, and interpolate the output mantissa using the retrieved samples and other information").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have additionally modified Lees and Koseljs invention of the method of claim 11, the accelerator sub-system, the display parameter, and the system memory with the features of Mombers invention of retrieving two or more look-up tables from system memory and interpolating between the two or more look-up tables. As demonstrated by Mombers, one could have indicated the ability to utilize some sort of table mapping that includes a series of memories where each memory is comprised of display parameters.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 2023/0343299) in view of Koselj et al. (U.S. Pub. No. 2005/0041039). as applied to claim 1 above, and further in view of Sinha et al. (U.S. Pub. No. 2015/0178136).
Regarding claim 10, Lee as modified by Koselj discloses the electronic device of claim 1 and the acceleration sub-system. Lee as modified by Koselj does not disclose a plurality of hardware accelerators.
However, in a similar field if endeavor, Sinha discloses a plurality of hardware accelerators (Sinha: FIG. 6; also, FIG. 11; also, paragraph 25, line(s) 5-8, "FIG. 6 is an example of a system having a series of Processor/Accelerator units 600, each of which has a Processor 610 and a series of Accelerators 630, interconnected by a Bus 620")
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have additionally modify Lees invention as modified by Koselj to include a plurality of hardware accelerators. As demonstrated by Koselj, when dealing with an acceleration sub-system, each component within a sub-system would be considered as dynamic, allowing the ability to implement additional hardware accelerators.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 2023/0343299) in view of Koselj et al. (U.S. Pub. No. 2005/0041039). as applied to claim 17 above, and further in view of Mombers (U.S. Pub. No. 2024/0036823) and Sinha et al. (U.S. Pub. No. 2015/0178136).
Regarding claim 20, Lee as modified by Koselj discloses the system of claim 17 and the accelerator sub-system, wherein the accelerator sub-system comprises: receiving the operating condition from the processor (Lee: paragraph 28, line(s) 12-19 " According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit or an application processor) and an auxiliary processor 123 (e.g., a graphic processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) capable of operating independently or together with the main processor."). Lee as modified by Koselj does not disclose an additional hardware accelerator, system memory configured to store a plurality of look-up tables, the process to retrieve two or more look-up tables of the plurality of look-up tables from the system memory; generate a combined look-up table by interpolating between the two or more look-up tables; and adjust the display parameter by writing the combined look-up table to the image processing circuitry.
However, in a similar field of endeavor, Mombers discloses a system memory configured to store a plurality of look-up tables (Mombers: paragraph 13, line(s) 8-19 "A lookup table may include an array of entries stored in memory where each entry includes one or more items of data. The array of entries may be indexed so that each entry has an associated index value that may be used to locate the entry within the array of entries and in memory to retrieve the one or more data items in the entry. According to aspects of the subject technology, the input mantissa from an input floating-point element may be used to index into lookup tables and the values retrieved from the lookup tables may be used to interpolate the output mantissa for the output floating-point element."; also, paragraph 24, line(s) 6-11 "The generated output mantissa is an estimate that is generated using the input mantissa to index lookup tables stored in memory 240, retrieve samples for the function and other information from the lookup tables, and interpolate the output mantissa using the retrieved samples and other information"), and the process to retrieve two or more look-up tables of the plurality of look-up tables from the system memory; generate a combined look-up table by interpolating between the two or more look-up tables; and adjust the display parameter by writing the combined look-up table to the image processing circuitry (Mombers: paragraph 13, line(s) 8-19 "A lookup table may include an array of entries stored in memory where each entry includes one or more items of data. The array of entries may be indexed so that each entry has an associated index value that may be used to locate the entry within the array of entries and in memory to retrieve the one or more data items in the entry. According to aspects of the subject technology, the input mantissa from an input floating-point element may be used to index into lookup tables and the values retrieved from the lookup tables may be used to interpolate the output mantissa for the output floating-point element."; also, paragraph 24, line(s) 6-11 "The generated output mantissa is an estimate that is generated using the input mantissa to index lookup tables stored in memory 240, retrieve samples for the function and other information from the lookup tables, and interpolate the output mantissa using the retrieved samples and other information") while Sinha discloses additional hardware accelerators (Sinha: FIG. 6; also, FIG. 11; also, paragraph 25, line(s) 5-8, "FIG. 6 is an example of a system having a series of Processor/Accelerator units 600, each of which has a Processor 610 and a series of Accelerators 630, interconnected by a Bus 620").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have additionally modify Lees invention as modified by Koselj of the system of claim 17, the accelerator sub-system, and the process to receive the operating condition from the processor with the features of Mombers invention of a system memory configured to store a plurality of look-up tables and the ability to retrieve two or more look-up tables of the plurality of look-up tables from the system memory; generate a combined look-up table by interpolating between the two or more look-up tables; and adjust the display parameter by writing the combined look-up table to the image processing circuitry and Sinhas invention of utilizing additional hardware accelerators. As demonstrated by Mombers and Sinhas, one could have included the support for indicating the use of some sort of mapping that can retrieve results from a look up table and generate a combined search; one could also add in the support for the use of an additional graphical accelerator.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 2023/0343299) in view of Koselj et al. (U.S. Pub. No. 2005/0041039), Mombers (U.S. Pub. No. 2024/0036823) and Sinha et al. (U.S. Pub. No. 2015/0178136), further in view of Mohtasham et al. (U.S. Pub. No. 20230336879),
Regarding claim 22, Lee in view of Koselj, Mombers, and Sinha discloses the system of claim 20, two or more look-up tables comprises bilinear interpolation or cubic interpolation.
However, in a similar field of endeavor, Mohtasham discloses wherein interpolating between the two or more look-up tables comprises bilinear interpolation or cubic interpolation (para 34, “In this example, the interpolation factor X 301 can be used, depending on the computed value of the interpolation factor X 301, as a ratio for interpolating (e.g., bilinear interpolation) between configuration information included in predetermined LUTs 320, 322, 324 and 326.”; also, para 51, “If the LUT engine 530 of the camera 500 includes one-thousand special purpose LUT ALUs 532, interpolation (e.g., bilinear interpolation) between the LUTs 522 and 524 could then be completed in a single operation cycle, with each of the one-thousand LUT ALUs 532 concurrently completing a single element-wise interpolation computation.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee's invention as modified by Koselj, Mombers, and Sinha of the accelerator sub-system, the system memory configured to store a plurality of look-up tables, and the generation of a combined look-up table by interpolating between the two or more look-up tables with the features of Mohtasham's invention of bilinear interpolation between predetermined look-up tables. A person of ordinary skill would have made this combination because Mohtasham teaches that dedicated hardware performing bilinear interpolation between predetermined look-up tables can complete the interpolation in a single operation cycle and offloads the computation from a general purpose processor, yielding the predictable result of a combined look-up table generated by bilinear interpolation for adjusting the display parameter of the image processing circuitry.
Response to Arguments
Applicant's arguments filed 06/11/2026 have been fully considered.
Regarding the rejection of claims 1-5, 7-9, 11, and 13-19 under 35 U.S.C. 103 over Lee in view of Koselj, Applicant argues (Remarks, page 4) that Lee discloses only selecting a specific time point within a period for transmitting image data from a graphics processing unit to a display driver and does not teach or suggest generating a display parameter based on an operating condition. This argument is not persuasive. Lee expressly teaches that "the processor 120 may be configured to determine pixel characteristic values included in the image data 620 based on the operating frequency. The pixel characteristic values may be values set for pixels included in a display panel (e.g., the display panel 210 in FIG. 2) to represent an image. For example, the pixel characteristic values may include, for example, a gamma characteristic value, a color ratio value, or an emission timing value.". Under the broadest reasonable interpretation, the operating frequency of the display driver integrated circuit is an operating condition, and the pixel characteristic values, including the gamma characteristic value, the color ratio value, and the emission timing value, are display parameters generated based on that operating condition.
Applicant further argues (Remarks, page 4) that Lee fails to teach or suggest configuring or adjusting the image processing circuitry and, more specifically, "writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry," as now recited in amended independent claims 1, 11, and 17, and that the Office action incorrectly equated the pre-processing or post-processing of the image processing module 235 of Lee with configuring or adjusting the image processing circuitry. This argument has been considered but is not persuasive, and it is moot in part because it does not respond to the mapping applied to the amended limitation in the current rejection, which was necessitated by Applicant's amendment. First, the argument attacks Lee individually, whereas the rejection is based on the combination of Lee in view of Koselj. Nonobviousness cannot be established by attacking references individually where the rejection is based on a combination of references, because the test for obviousness is what the combined teachings of the references would have suggested to one of ordinary skill in the art. In the current rejection, Koselj, not Lee, is relied upon for the writing limitation: Koselj expressly teaches that "A set of control/status registers is used to control the operation of the circuit. Host CPU writes values to control registers (via the interface circuit) to assign mode of operation and instruct circuitry what to do with consequent data coming from host CPU." and that "data transfer can be writing to a control register (control logic) to instruct the operation of the circuitry". Second, the amended limitation is recited in the alternative, requiring writing the display parameter to at least one circuit block of the image processing circuitry or at least one register of the image processing circuitry. Under MPEP 2111.04, only one of the recited alternatives need be taught by the prior art to meet the limitation; Koselj's express teaching of writing values to control registers of the display driver circuitry meets the register alternative. Third, Lee itself is not limited to transmission timing: Lee teaches that "the DDI 230 may store at least part of the received image information in the memory 233, for example, in units of frames" and that "The DDI 230 may store image data transmitted by the processor 120 in the frame buffer 320", where the pixel characteristic values determined based on the operating frequency are included in the image data delivered into the memory of the display driver integrated, which under the broadest reasonable interpretation is a writing of parameter-bearing data into a circuit block of the image processing circuitry.
Applicant argues (Remarks, page 4) that Koselj discloses only a graphics engine integrated into a display module for processing graphics commands and rendering image data for display and does not remedy the deficiencies of Lee. This argument is not persuasive for the reasons stated above: Koselj is relied upon for the acceleration sub-system and for writing values to at least one register of the circuitry to configure its operation, and no deficiency remains to be remedied.
Applicant's arguments regarding dependent claims 2, 3, 5, 7-9, 13-15, 18, and 19, and regarding dependent claims 6, 10, 12, and 20 (Remarks, pages 4-5), rest entirely on the asserted allowability of independent claims 1, 11, and 17 and on the assertion that Mombers and Sinha do not cure the deficiencies of Lee and Koselj. Because the arguments directed to the independent claims are not persuasive, these dependent arguments are likewise not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jai Li whose telephone number is (571)272-1170. The examiner can normally be reached Mon-Thu between 06:00-16:00 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu can be reached at (571)272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAI W LI/Junior Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613
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