DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Amendment filed on 02/13/2026.
In the instant Amendment, claims 1, 11 and 20 have been amended; and claims 1, 11 and 20 are independent claims. Claims 1-20 have been examined and are pending. This Action is made FINAL.
Response to Arguments
Applicants’ arguments in the instant Amendment, filed on 02/13/2026, with respect to limitations listed below, have been fully considered but they are not persuasive.
Applicant’s arguments: “Bernat fails to disclose the limitation "a trusted chip and performing, by the trusted chip, trust authentication on a component after receiving an authentication success message from the authentication node, wherein the component comprises an input/output (I/O) unit and a storage unit, and wherein the trusted chip and the component are included in a server, and the trusted chip and the component establish a communication connection through a bus".”
The Examiner disagrees with the Applicants. The Examiner respectfully submits that Bernat discloses Bernat in view of Li discloses aforementioned limitations (Bernat: par. 0030 in block 318, the edge appliance device 102a may verify the component certificate of the component 206. The edge appliance device 102a may verify the certificate [] the edge appliance device 102a may verify the certificate using the public key of the Device Identifier of the component 206; par. 0013 the illustrative edge device 102 includes a compute engine 120, an I/O subsystem 122, a memory 124, a data storage device 126; par. 0026 each attestation manager 202 may forward attestations originating from an attester 208 or each attestation manager 202 may aggregate the attestations into a simplified attestation statement that speaks on behalf of the platform verification result). More specifically, Bernat discloses a system 100 for accelerated orchestration and attestation includes multiple edge devices 102 and multiple endpoint devices 104. In use, as described further below, one or more edge devices 102 may be composed into or otherwise establish an edge appliance device 102 to perform a function-as-a-service (FaaS) request or other service. The edge appliance device 102 generates an appliance certificate using accelerated logic. The appliance certificate attests to the configuration and utilization of one or more components of the edge appliance device 102. The edge appliance device 102 provides the appliance certificate to an orchestrator, such as an edge orchestrator device 102. The edge orchestrator device 102 verifies the appliance certificate and compares the appliance certificate to a service level agreement (SLA) requirement associated with a tenant workload. Thus, the system 100 allows for verification of the complete root of trust for components of an edge appliance [par: 0012]. However, Li discloses the trusted chip and the component are included in a server, and the trusted chip and the component establish a communication connection through a bus (Li: par. 0026 a trusted platform control module (TPCM), configured to establish and secure trusted sources and provide trusted platform control; fig. 4; par. 0093 the server includes parts such as a central processing unit, a baseboard management controller, a Boot Rom, a BMC Flash, a sequential control circuit and a trusted platform control module; par. 0064 the SPI trusted measurement interface module is configured to enable the SPI bus function, and devices such as the Boot Rom and the BMC Flash of the server are accessed through the SPI). More specifically, Li discloses an external serial peripheral interface (serial peripheral interface) bus, this method imposes a great challenge to signal quality and is unstable though with reduced costs for chips of the trusted platform control module and accomplishment of transfer for a single trusted chain [par. 0092] and a related technology can be that TPCM trusted modules on both the intelligence board and the server are regarded as trusted modules measuring their respective systems [par. 0093]. Therefore, the examiner finds this argument not persuasive.
The amended claims 1, 11 and 20 have been addressed in rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8, 10-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bernat et al. (“Bernat,” US 2019/0230002) in view of LI (“Li,” US 2025/0165422).
Regarding claim 1: Bernat discloses a trust computing method, wherein the method comprises:
sending, an authentication request to an authentication node, wherein the authentication request comprises a request for the authentication node to perform trust authentication (Bernat: par. 0014 a system-on-a-chip (SoC) and [] a single integrated circuit chip; par. 0024 the aggregated attestation manager 224 is configured to receive an appliance certificate from an edge appliance device 102a [] the aggregated attestation manager 224 is further configured to verify the appliance certificate); and
performing, trust authentication on a component after receiving an authentication success message from the authentication node, wherein the component comprises an input/output (I/O) unit and a storage unit (Bernat: par. 0030 in block 318, the edge appliance device 102a may verify the component certificate of the component 206. The edge appliance device 102a may verify the certificate [] the edge appliance device 102a may verify the certificate using the public key of the Device Identifier of the component 206; par. 0013 the illustrative edge device 102 includes a compute engine 120, an I/O subsystem 122, a memory 124, a data storage device 126; par. 0026 each attestation manager 202 may forward attestations originating from an attester 208 or each attestation manager 202 may aggregate the attestations into a simplified attestation statement that speaks on behalf of the platform verification result).
Bernat does not explicitly disclose a trusted chip and wherein the trusted chip and the component are included in a server, and the trusted chip and the component establish a communication connection through a bus.
However, Li discloses a trusted chip (Li: par. 0026 a trusted platform control module (TPCM), configured to establish and secure trusted sources and provide trusted platform control); and
wherein the trusted chip and the component are included in a server, and the trusted chip and the component establish a communication connection through a bus (Li: fig. 4; par. 0093 the server includes parts such as a central processing unit, a baseboard management controller, a Boot Rom, a BMC Flash, a sequential control circuit and a trusted platform control module; par. 0064 the SPI trusted measurement interface module is configured to enable the SPI bus function, and devices such as the Boot Rom and the BMC Flash of the server are accessed through the SPI).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Li with the system/method of Bernat to include the trusted chip and the component are included in a server, and the trusted chip and the component establish a communication connection through a bus. One would have been motivated to performing trusted measurement on the target data to obtain a measurement result, where when the measurement result indicates that the server is trusted (Li: par. 0007).
Regarding claim 2: Bernat in view of Li discloses the method according to claim 1.
Bernat further discloses wherein the authentication request comprises a first certificate, the first certificate is generated by the trusted chip based on a preset first key, and the first certificate is used by the authentication node to perform trust authentication on the first certificate based on a first preset certificate (Bernat: par. 0028 during the attestation procedure, in block 316 the edge appliance device 102a receives a component certificate from the component 206. The component certificate includes a verifiable assertion of the identity and configuration of the component 206 [] the component certificate may be indicative of particular security attributes of a trusted execution environment provided by the edge appliance device 102a [] such as secret keys or other sensitive data; par. 0029 the edge appliance device 102a and the component 206 may perform any appropriate attestation protocol).
Regarding claim 3: Bernat in view of Li discloses the method according to claim 2.
Bernat further discloses wherein the performing, by the trusted chip, trust authentication on the component comprises: receiving, by the trusted chip, a second certificate sent by the component, wherein the second certificate is generated by the component based on a preset second key (Bernat: par. 0029 the component 206 derives an asymmetric key pair based on the CDI that is used as a device identity for the component 206, and generates a certificate based on that key pair); and
performing, by the trusted chip, trust authentication on the second certificate based on a second preset certificate (Bernat: par. 0030 the edge appliance device 102a may verify the certificate using the public key of the Device Identifier of the component 206).
Regarding claim 4: Bernat in view of Li discloses the method according to claim 3.
Bernat further discloses wherein the preset first key indicates integrity of the trusted chip (Bernat: par. 0028 the security attributes may indicate cryptographic or isolation protections available to code or data processed by the edge appliance device 102a, such as secret keys), and the preset second key indicates integrity of the component (Bernat: par. 0029 the component 206 derives an asymmetric key pair based on the CDI that is used as a device identity for the component 206, and generates a certificate based on that key pair).
Regarding claim 5: Bernat in view of Li discloses the method according to claim 1.
Bernat further discloses sending, by the trusted chip, a first measurement request to the authentication node, wherein the first measurement request is used by the authentication node to perform trust measurement on the trusted chip (Bernat: par. 0031 in block 320, the edge appliance device 102a may receive certified telemetry 214 from the component 206. The certified telemetry 214 is indicative of utilization of the component 206. For example, the telemetry 214 may indicate processor utilization of a compute engine 120, memory or storage utilization, or other utilization statistics); and
performing, by the trusted chip, trust measurement on the component (Bernat: par. 0031 the telemetry 214 may be certified by the component 206, for example by being signed with the device identifier [] the edge appliance device 102a may verify the certified telemetry 214, for example using the device certificate).
Regarding claim 6: Bernat in view of Li discloses the method according to claim 1.
Bernat further discloses wherein before the sending, by the trusted chip, an authentication request to the authentication node, the method further comprises: performing, by the trusted chip, integrity check on firmware of the trusted chip (Bernat: par. 0020 the attestation process generates a component certificate for each component 206. The component certificate is indicative of firmware 210 of the component 206 and/or a hardware or firmware configuration 212 of the component 206).
Regarding claim 8: Bernat in view of Li discloses the method according to claim 1.
Bernat further discloses wherein the I/O unit comprises a network adapter or a Peripheral Component Interconnect Express (PCIE) riser (Bernat: par. 0016 a high-speed connection interface such as a peripheral bus ( e.g., a PCI Express bus)); and
the storage unit comprises one or more of a hard disk backplane, an extension unit, or a PCIE switch (Bernat: par. 0015 the data storage device 126 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives).
Regarding claim 10: Bernat in view of Li discloses the method according to claim 1.
Li further discloses wherein the trusted chip is integrated into a baseboard management controller (BMC) chip of the server (Li: par. 0030 The trusted platform control module (TPCM) is integrated in a trusted computing platform [] as a BMC Boot Rom), or the trusted chip is connected to the BMC chip through an external bus.
The motivation is the same that of claim 1 above.
Regarding claim 11: Bernat discloses a chip, wherein the chip comprises:
an interface, configured to send an authentication request to an authentication node, wherein the authentication request comprises a request for the authentication node to perform trust authentication on the chip (Bernat: par. 0016 the accelerator 130 may be incorporated in or otherwise coupled with one or more other components of the edge device 102, such as a network interface controller (NIC) of the communication subsystem 128; par. 0024 the aggregated attestation manager 224 is configured to receive an appliance certificate from an edge appliance device 102a [] the aggregated attestation manager 224 is further configured to verify the appliance certificate); and
at least one processor, configured to perform trust authentication on a component, wherein the component comprises an input/output (I/O) unit and a storage unit after receiving an authentication success message from the authentication node (Bernat: par. 0016 a coprocessor; par. 0030 in block 318, the edge appliance device 102a may verify the component certificate of the component 206. The edge appliance device 102a may verify the certificate [] the edge appliance device 102a may verify the certificate using the public key of the Device Identifier of the component 206; par. 0013 the illustrative edge device 102 includes a compute engine 120, an I/O subsystem 122, a memory 124, a data storage device 126; par. 0026 each attestation manager 202 may forward attestations originating from an attester 208 or each attestation manager 202 may aggregate the attestations into a simplified attestation statement that speaks on behalf of the platform verification result).
Bernat does not explicitly disclose wherein the chip and the component are included in a server, and the chip and the component establish a communication connection through a bus.
However, Li discloses wherein the chip and the component are included in a server, and the chip and the component establish a communication connection through a bus (Li: fig. 4; par. 0093 the server includes parts such as a central processing unit, a baseboard management controller, a Boot Rom, a BMC Flash, a sequential control circuit and a trusted platform control module; par. 0064 the SPI trusted measurement interface module is configured to enable the SPI bus function, and devices such as the Boot Rom and the BMC Flash of the server are accessed through the SPI).
Regarding claims 12-16: Claims 12-16 are similar in scope to claims 2-6, respectively, and are therefore rejected under similar rationale.
Regarding claim 18: Claim 18 is similar in scope to claim 8, and is therefore rejected under similar rationale.
Regarding claim 20: Bernat discloses a server, wherein the server comprises a trusted chip and a component;
send an authentication request to an authentication node, wherein the authentication request comprises a request for the authentication node to perform trust authentication (Bernat: par. 0014 a system-on-a-chip (SoC) and [] a single integrated circuit chip; par. 0024 the aggregated attestation manager 224 is configured to receive an appliance certificate from an edge appliance device 102a [] the aggregated attestation manager 224 is further configured to verify the appliance certificate); and
perform trust authentication on the component after receiving an authentication success message from the authentication node, wherein the component comprises an input/output (I/O) unit and a storage unit (Bernat: par. 0030 in block 318, the edge appliance device 102a may verify the component certificate of the component 206. The edge appliance device 102a may verify the certificate [] the edge appliance device 102a may verify the certificate using the public key of the Device Identifier of the component 206; par. 0013 the illustrative edge device 102 includes a compute engine 120, an I/O subsystem 122, a memory 124, a data storage device 126; par. 0026 each attestation manager 202 may forward attestations originating from an attester 208 or each attestation manager 202 may aggregate the attestations into a simplified attestation statement that speaks on behalf of the platform verification result).
Bernat does not explicitly disclose a trusted chip.
However, Li discloses a trusted chip (Li: par. 0026 a trusted platform control module (TPCM), configured to establish and secure trusted sources and provide trusted platform control).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Li with the system/method of Bernat to include a trusted chip. One would have been motivated to performing trusted measurement on the target data to obtain a measurement result, where when the measurement result indicates that the server is trusted (Li: par. 0007).
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bernat et al. (“Bernat,” US 2019/0230002) in view of LI (“Li,” US 2025/0165422) and VOLOS et al. (“Volos,” US 2020/0125772).
Regarding claim 7: Bernat in view of Li discloses the method according to claim 1.
Bernat in view of Li does not explicitly disclose wherein the method further comprises: clearing, by the trusted chip, sensitive data in the component when the component is replaced.
However, Volos discloses wherein the method further comprises: clearing, by the trusted chip, sensitive data in the component when the component is replaced (Volos: par. 0082 when the TEE is explicitly terminated, or the peripheral device receives a reset signal from the host, the security module deletes all sensitive data and returns the peripheral device to a clean state).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Volos with the system/method of Bernat and Li to include clearing, by the trusted chip, sensitive data in the component when the component is replaced. One would have been motivated to form a trusted execution environment on the peripheral device for processing sensitive data using sensitive code (Volos: par. 0005).
Regarding claim 17: Claim 17 is similar in scope to claim 7, and is therefore rejected under similar rationale.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bernat et al. (“Bernat,” US 2019/0230002) in view of LI (“Li,” US 2025/0165422), Trautman et al. (“Trautman,” US 2008/0005591) and JACQUIN et al. (“Jacquin,” US 2022/0278855).
Regarding claim 9: Bernat in view of Li discloses the method according to claim 1.
Bernat further discloses wherein the component comprises an acceleration unit (Bernat: par. 0022 an accelerator 130), a memory expansion unit (Bernat: par. 0022 a memory device 124 (e.g., a DIMM or other memory component)), wherein
the acceleration unit comprises a carrier board and an acceleration card interconnection switch (Bernat: par. 0021 the platform verifier 204 is implemented in an accelerator 130 such as an FPGA), and
the memory expansion unit comprises a carrier board, and the memory expansion unit further comprises one or more of a memory expansion chip, a dual in-line memory module (DIMM), or a storage class memory (SCM) medium (Bernat: par. 0022 each component 206 may be embodied as a compute engine 120 or other compute platform (e.g., processor, SoC, or other compute element and motherboard or other associated circuit board), a memory device 124 (e.g., a DIMM or other memory component)).
Li further discloses a computing unit (Li: par. 0043 a central processing unit (CPU)), wherein
the computing unit comprises a central processing unit (CPU) (Li: par. 0043 a central processing unit (CPU)), and a power supply (Li: par. 0074 a power supply).
The motivation is the same that of claim 1 above.
Bernat in view of Li does not explicitly disclose a cooling unit, a double data rate (DDR) synchronous dynamic random access memory and the cooling unit comprises at least one of air cooling device or liquid cooling device.
However, Trautman discloses a cooling unit (Trautman: fig. 10 cooling device item 1020),
a double data rate (DDR) synchronous dynamic random access memory (Trautman: par. 0065 Memory 1015 may comprise any type of memory for storing data, including [] a Double Data Rate Random Access Memory); and
the cooling unit comprises at least one of air cooling device or liquid cooling device (Trautman: par. 0065 cooling device 1020 may include a fan).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Trautman with the system/method of Bernat and Li to include a cooling unit, a double data rate (DDR) synchronous dynamic random access memory and air cooling device or liquid cooling device. One would have been motivated to provide security, reliability, and efficient operation of a device, system, platform, or operating environment (Trautman: par. 0001).
Bernat in view of Li and Trautman does not explicitly disclose wherein an acceleration card comprises one or more of a graphics processing unit (GPU), a data processing unit (DPU), or a neural-network processing unit (NPU).
However, Jacquin discloses wherein an acceleration card comprises one or more of a graphics processing unit (GPU), a data processing unit (DPU), or a neural-network processing unit (NPU) (Jacquin: par. 0022 multiple graphics processing unit (GPU)).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Jacquin with the system/method of Bernat, Li and Trautman to include an acceleration card comprises one or more of a graphics processing unit (GPU), a data processing unit (DPU), or a neural-network processing unit (NPU). One would have been motivated to authenticate the platform by verifying the secure device identifiers and ensuring that the platform has the required identity certificates while deploying the platform (Jacquin: par. 0001).
Regarding claim 19: Claim 19 is similar in scope to claim 9, and is therefore rejected under similar rationale.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAHIMEH MOHAMMADI/ Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439