DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “one or more second conductive structures coupled with the one or more conductive structures [vias] at the second surface” of claims 2, 10, and 17, “the one or more second conductive structures comprise solder” of claims 3, 11, and 18, the “one or more second redistribution layers parallel to and contacting the second surface” of claims 9 and 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claims 1, 4-9, 12-16, and 19-20 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Kim (US Pub. No. 2008/0308921).
Regarding claim 1, in FIG. 5, Kim discloses a semiconductor device assembly, comprising: an encapsulant material (440) comprising a first surface (top) and a second surface (bottom) opposite the first surface; a semiconductor device (410) embedded within the encapsulant material and comprising a third surface (top) and a fourth surface (bottom) opposite the third surface, wherein the third surface is coplanar with the first surface; one or more conductive structures (430) extending through the encapsulant material from about the first surface to about the second surface; one or more first conductive layers (432) coplanar with the first surface and the third surface, wherein the one or more first conductive layers are configured to couple the one or more conductive structures with the semiconductor device; and one or more second conductive layers (bottom 432/422) coplanar with the second surface.
Regarding claim 4, in FIG. 5, Kim discloses that the semiconductor device comprises one or more bond pads (412) at the third surface.
Regarding claim 5, in FIG. 5, Kim discloses that the one or more first conductive layers comprise a conductive line coupled with the one or more bond pads of the semiconductor device.
Regarding claim 6, in FIG. 5, Kim discloses that the one or more conductive structures each comprise a conductive via.
Regarding claim 7, in FIG. 5, Kim discloses that the one or more first conductive layers comprise a first redistribution layer, and the one or more second conductive layers comprise a second redistribution layer.
Regarding claim 8, in FIG. 5, Kim discloses that the semiconductor device comprises a semiconductor die.
Regarding claim 9, in FIG. 5, Kim discloses a semiconductor device assembly, comprising: an encapsulant material (440) comprising a first surface (top) and a second surface (bottom) opposite the first surface; a semiconductor device (410) embedded within the encapsulant material and comprising a third surface (top) and a fourth surface (bottom) opposite the third surface, wherein the third surface is parallel to and contacting the first surface; one or more conductive structures (430) extending through the encapsulant material from the first surface to the second surface, wherein the one or more conductive structures are perpendicular to the first surface; one or more first redistribution layers (432) parallel to the first surface and contacting the third surface, wherein the one or more first redistribution layers are configured to couple the one or more conductive structures with the semiconductor device; and one or more second redistribution layers (bottom 432/422) parallel to and contacting the second surface.
Regarding claim 12, in FIG. 5, Kim discloses that the semiconductor device comprises one or more bond pads (412) at the third surface.
Regarding claim 13, in FIG. 5, Kim discloses that the one or more first redistribution layers comprise a conductive line coupled with the one or more bond pads of the semiconductor device.
Regarding claim 14, in FIG. 5, Kim discloses that the one or more conductive structures each comprise a conductive via.
Regarding claim 15, in FIG. 5, Kim discloses that the semiconductor device comprises a semiconductor die.
Regarding claim 16, in FIG. 5, Kim discloses a semiconductor device assembly, comprising: an encapsulant material (440) comprising a first surface (top) and a second surface (bottom) opposite the first surface; a semiconductor die (410) embedded within the encapsulant material and comprising a third surface (top) and a fourth surface (bottom) opposite the third surface, wherein the third surface is coplanar with the first surface; one or more conductive vias (430) extending through the encapsulant material from the first surface to the second surface; one or more first redistribution layers (432) parallel to the first surface and contacting the third surface, wherein the one or more first redistribution layers are configured to couple the one or more conductive vias with the semiconductor die; and one or more second redistribution layers (bottom 432) parallel to and contacting the second surface.
Regarding claim 19, in FIG. 5, Kim discloses that the semiconductor die comprises one or more bond pads (412) at the third surface.
Regarding claim 20, in FIG. 5, Kim discloses that the one or more first redistribution layers comprise a conductive line coupled with the one or more bond pads of the semiconductor die.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 10-11, and 17-18 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kim (US Pub. No. 2008/0308921) in view of Farnworth (US Patent No. 6,020,629).
Regarding claims 2-3 and 10-11, Kim appears not to explicitly disclose one or more second conductive structures coupled with the one or more conductive structures at the second surface.
The art however well recognized one or more second conductive structures coupled with one or more conductive structures at a second surface to be suitable for use in connecting adjacent semiconductor device assemblies. See, for example, Farnworth, FIG. 2D, element (42RF).
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious to a person of ordinary skill in the art at the time of invention to have formed one or more second conductive structures (solder) coupled with the one or more conductive structures at the second surface for its recognized suitability in connecting adjacent semiconductor device assemblies. In doing so, the one or more second conductive structures comprise solder.
Regarding claims 17-18, Kim appears not to explicitly disclose one or more second conductive structures coupled with the one or more conductive vias at the second surface.
The art however well recognized one or more second conductive structures coupled with one or more conductive vias at a second surface to be suitable for use in connecting adjacent semiconductor device assemblies. See, for example, Farnworth, FIG. 2D, element (42RF).
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious to a person of ordinary skill in the art at the time of invention to have formed one or more second conductive structures (solder) coupled with the one or more conductive vias at the second surface for its recognized suitability in connecting adjacent semiconductor device assemblies. In doing so, the one or more second conductive structures comprise solder.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
