Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 20, it is dependent on claim 15, however, it should be dependent on claim 17, because “ cut region portions ” are claimed in claim 17, not claim 15. Please clarify it. For examination purpose, examiner is assuming claim 20 is dependent on claim 17 as suggested above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 8 – 10, 15 – 16, 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang ( Pub. No. US 20230058880 A1 ), hereinafter Chang.
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Regarding Independent Claim 1 (Currently Amended), Chang teaches a device comprising:
a plurality of memory cells ( Chang, FIG. 1, 102; [0017], memory cells 102 ), each memory cell including:
a diffusion region ( Chang, FIG. 4, 410, 410a; [0031], An active area such as an oxide diffusion (i.e., OD) region 410a (the OD layer is denoted as 410) ) formed in a substrate; and
a plurality of transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b; [0024], a first transistor 202 connected in series with a second transistor 204 … antifuse transistor 202 … selection transistor 204; [0032], Four metal gate (i.e., MG) strips 420a, 420b, 420c, and 420d (the MG layer is denoted as 420) are disposed over the OD region 410a ) fabricated over the diffusion region ( Chang, FIG. 4, 410, 410a ), wherein:
each transistor ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) includes one or more source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c; [0033], Three metal-over-diffusion (i.e., MD) strips 430a, 430b, and 430c (the MD layer is denoted as 430) are disposed over the OD region 410a … MD strip 430a serves as a source/drain contact structure of both the antifuse transistor 202a and the selection transistor 204a; the MD strip 430c serves as a source/drain contact structure of the antifuse transistor 202b and the selection transistor 204b. The MD strip 430b serves as a source/drain contact structure of the selection transistor 204a and the selection transistor 204b ) and one or more gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d; [0032], Four metal gate (i.e., MG) strips 420a, 420b, 420c, and 420d (the MG layer is denoted as 420) … WLP signal WLP0 can be applied to the metal gate strip 420a … WLR signal WLR0 can be applied to the metal gate strip 420b … WLR signal WLR1 can be applied to the metal gate strip 420c … WLP signal WLP1 can be applied to the metal gate strip 420d );
the source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c ) and the gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) are arranged along a first direction ( Chang, FIG. 4, x direction ), each extend in a second direction ( Chang, FIG. 4, y direction ) transverse to the first direction ( Chang, FIG. 4, x direction ), and overlap the diffusion region ( Chang, FIG. 4, 410, 410a ) in a third direction ( Chang, FIG. 4, z direction ) transverse to the first ( Chang, FIG. 4, x direction ) and second ( Chang, FIG. 4, y direction ) directions; and
gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of an adjacent pair of memory cells are free of a source/drain contact ( Chang, [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) therebetween and have substantially the same contact poly pitch (CPP) as an adjacent pair of gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of a memory cell ( Chang, FIG. 1, 102 ).
Regarding Claim 2 (Original), Chang teaches the device as claimed in claim 1, on which this claim is dependent, Chang further teaches:
the memory cell ( Chang, FIG. 1, 102; FIG. 2, FIG. 3, FIG. 4 ) is a 2 CPP ( Chang, FIG. 4, 460a to 430b is 2 CPP; [0015], Typically, an OTP memory device using antifuse has a two-transistor (2T) per bit arrangement ) memory cell;
the plurality of the transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) further include a first source/drain contact ( Chang, FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460) correspond to the vacancy terminal 203a and the vacancy terminal 203b ) connected to a floating source/drain terminal ( Chang, FIG. 4, 460a, 460b; [0015], However, one source/drain terminal of the antifuse transistor is a floating terminal (i.e., not connected to any other components); [0034], as the first terminal 203a of the antifuse transistor 202a and the first terminal 203b of the antifuse transistor 202b are floating terminals ) and a second source/drain contact ( Chang, FIG. 4, 430a, 430c; [0033] Three metal-over-diffusion (i.e., MD) strips 430a, 430b, and 430c (the MD layer is denoted as 430) are disposed over the OD region 410a and extend in the Y direction. The MD strip 430a serves as a source/drain contact structure … the MD strip 430c serves as a source/drain contact structure ) connected to a bit line ( Chang, FIG. 2, BL 112; FIG. 4, 430a, 430b, 430c; [0029], The OTP memory cells 102a and 102b share a bit line (not shown in FIG. 3 for simplicity) that receives a signal BL0; [0036], The MD strip 430b is connected to the MO strip 440a through an MD via (i.e., VD) 450a (collectively 450). As such, the MO strip 440a serves as the metal strip for the bit line signal BL0 ); and
the first ( Chang, FIG. 4, 460a, 460b ) and second ( Chang, FIG. 4, 430a, 430c ) source/drain contacts have a CPP of 1 unit ( Chang, FIG. 4, 460a to 430a is 1 CPP, 460b to 430c is 1 CPP ).
Regarding Claim 3 (Original), Chang teaches the device as claimed in claim 1, on which this claim is dependent, Chang further teaches: wherein:
the memory cell ( Chang, FIG. 1, 102; FIG. 2, FIG. 3, FIG. 4 ) is a 3 CPP ( Chang, FIG. 4, 460a to 430c is 3 CPP ) memory cell;
the plurality of the transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) include:
a first source/drain contact ( Chang, FIG. 4, 460a, 460b; [0034] ) connected to a floating source/drain ( Chang, FIG. 4, 460a, 460b; [0015] ) terminal;
a second source/drain contact ( Chang, FIG. 4, 430b; [0033] ) connected to a bit line ( Chang, [0036], The MD strip 430b is connected to the MO strip 440a through an MD via (i.e., VD) 450a (collectively 450). As such, the MO strip 440a serves as the metal strip for the bit line signal BL0 );
a third source/drain contact ( Chang, FIG. 4, 430a, 430c; [0033] ) between the first ( Chang, FIG. 4, 460a, 460b; [0034] ) and second ( Chang, FIG. 4, 430b; [0033] ) source/drain contacts;
the first ( Chang, FIG. 4, 460a, 460b; [0034] ) and third ( Chang, FIG. 4, 430a, 430c; [0033] ) source/drain contacts have a CPP of 1 unit ( Chang, FIG. 4, 460a to 430a is 1 CPP; 460b to 430b is 1 CPP ); and
the second ( Chang, FIG. 4, 430b; [0033] ) and third ( Chang, FIG. 4, 430a, 430c; [0033] ) source/drain contacts have a CPP of 1 unit ( Chang, FIG. 4, 430b to 430a is 1 CPP; 430b to 430b is 1 CPP ).
Regarding Independent Claim 8 (Currently Amended), Chang teaches a device comprising:
a plurality of memory cells ( Chang, FIG. 1, 102; [0017], memory cells 102 ), each memory cell including:
a first diffusion region ( Chang, FIG. 4, 410, 410a; [0031], An active area such as an oxide diffusion (i.e., OD) region 410a (the OD layer is denoted as 410) ) formed in a substrate; and
a plurality of transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b; [0024], a first transistor 202 connected in series with a second transistor 204 … antifuse transistor 202 … selection transistor 204; [0032], Four metal gate (i.e., MG) strips 420a, 420b, 420c, and 420d (the MG layer is denoted as 420) are disposed over the OD region 410a ) fabricated over the first diffusion region ( Chang, FIG. 4, 410, 410a ), wherein:
each transistor( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) includes one or more source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c; [0033], Three metal-over-diffusion (i.e., MD) strips 430a, 430b, and 430c (the MD layer is denoted as 430) are disposed over the OD region 410a … MD strip 430a serves as a source/drain contact structure of both the antifuse transistor 202a and the selection transistor 204a; the MD strip 430c serves as a source/drain contact structure of the antifuse transistor 202b and the selection transistor 204b. The MD strip 430b serves as a source/drain contact structure of the selection transistor 204a and the selection transistor 204b ) and one or more gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d; [0032], Four metal gate (i.e., MG) strips 420a, 420b, 420c, and 420d (the MG layer is denoted as 420) … WLP signal WLP0 can be applied to the metal gate strip 420a … WLR signal WLR0 can be applied to the metal gate strip 420b … WLR signal WLR1 can be applied to the metal gate strip 420c … WLP signal WLP1 can be applied to the metal gate strip 420d );
the source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c ) and the gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) are arranged along a first direction ( Chang, FIG. 4, x direction ), each extend in a second direction ( Chang, FIG. 4, y direction ) transverse to the first direction ( Chang, FIG. 4, x direction ), and overlap the first diffusion region ( Chang, FIG. 4, 410, 410a ) in a third direction ( Chang, FIG. 4, z direction ) transverse to the first ( Chang, FIG. 4, x direction ) and second ( Chang, FIG. 4, y direction ) directions; and
gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of an adjacent pair of transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) are free of a source/drain contact ( Chang, [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) therebetween and have substantially the same contact poly pitch (CPP) as an adjacent pair of gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of a transistor ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ).
Regarding Claim 9 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent, Chang further teaches:
the memory cell ( Chang, FIG. 1, 102; FIG. 2, FIG. 3, FIG. 4 ) is a 2 CPP ( Chang, FIG. 4, 460a to 430b is 2 CPP; [0015], Typically, an OTP memory device using antifuse has a two-transistor (2T) per bit arrangement )memory cell;
the plurality of the transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) further include a source/drain terminal ( Chang, FIG. 4, 460a, 460b; [0015], However, one source/drain terminal of the antifuse transistor is a floating terminal (i.e., not connected to any other components); [0034], as the first terminal 203a of the antifuse transistor 202a and the first terminal 203b of the antifuse transistor 202b are floating terminals ) and first and second source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c; [0033] ) connected to the source/drain terminal; and
the first and second source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c; [0033] ) have a CPP of 1 unit ( Chang, FIG. 4, 430b to 430a is 1 CPP, 430b to 430c is 1 CPP ) .
Regarding Claim 10 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent, Chang further teaches: wherein:
the memory cell ( Chang, FIG. 1, 102; FIG. 2, FIG. 3, FIG. 4 ) is a 3 CPP ( Chang, FIG. 4, 460a to 430c is 3 CPP ) memory cell;
the plurality of the transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) further include:
a first source/drain contact ( Chang, FIG. 4, 460a, 460b; [0034] );
a second source/drain contact ( Chang, FIG. 4, 430b; [0033] ) connected to a bit line ( Chang, [0036], The MD strip 430b is connected to the MO strip 440a through an MD via (i.e., VD) 450a (collectively 450). As such, the MO strip 440a serves as the metal strip for the bit line signal BL0 );
a third source/drain contact ( Chang, FIG. 4, 430a, 430c; [0033] ) between the first ( Chang, FIG. 4, 460a, 460b; [0034] ) and second ( Chang, FIG. 4, 430b; [0033] ) source/drain contacts;
the first ( Chang, FIG. 4, 460a, 460b; [0034] ) and third ( Chang, FIG. 4, 430a, 430c; [0033] ) source/drain contacts have a CPP of 1 unit ( Chang, FIG. 4, 460a to 430a is 1 CPP; 460b to 430b is 1 CPP ); and
the second ( Chang, FIG. 4, 430b; [0033] ) and third ( Chang, FIG. 4, 430a, 430c; [0033] ) source/drain contacts have a CPP of 1 unit ( Chang, FIG. 4, 430b to 430a is 1 CPP; 430b to 430b is 1 CPP ).
Regarding Independent Claim 15 (Currently Amended), Chang teaches a method of manufacturing a memory device, the method comprising:
forming a diffusion region ( Chang, FIG. 4, 410, 410a ) in a substrate;
fabricating a plurality of transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) over the diffusion region ( Chang, FIG. 4, 410, 410a ), wherein:
each transistor ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ) includes one or more source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c ) and one or more gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ); and
the source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c ) and the gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) are arranged along a first direction ( Chang, FIG. 4, x direction ), each extend in a second direction ( Chang, FIG. 4, y direction ) transverse to the first direction ( Chang, FIG. 4, x direction ), and overlap the diffusion region in a third direction ( Chang, FIG. 4, z direction ) transverse to the first ( Chang, FIG. 4, x direction )and second ( Chang, FIG. 4, y direction ) directions; and
forming a plurality of memory cells ( Chang, FIG. 1, 102 ), each including the plurality of transistors ( Chang, FIG. 2, FIG. 4, 202, 204, 202a, 202b, 204a, 204b ), such that gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of an adjacent pair of memory cells have a smaller contact poly pitch (CPP) than a memory cell ( Chang, FIG. 1, 102 ).
Regarding Claim 16 (Original), Chang teaches the method as claimed in claim 15, Chang further teaches: wherein:
the memory cell ( Chang, FIG. 1, 102; FIG. 2, FIG. 3, FIG. 4 ) is a 2 CPP ( Chang, FIG. 4, 460a to 430b is 2 CPP ) memory cell or greater; and
the gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) of an adjacent pair of memory cells have a CPP of 1 unit ( Chang, FIG. 4, 420b to 420c is 1 CPP ).
Regarding Claim 19 (Original), Chang teaches the method as claimed in claim 15, Chang further teaches: further comprising:
implanting a dopant in the diffusion region to form a floating source/drain region ( Chang, FIG. 4, 460a, 460b; [0015], However, one source/drain terminal of the antifuse transistor is a floating terminal (i.e., not connected to any other components); [0034], as the first terminal 203a of the antifuse transistor 202a and the first terminal 203b of the antifuse transistor 202b are floating terminals ); and
connecting a source/drain contact ( Chang, FIG. 4, 430a, 430c ) to the floating source/drain region ( Chang, FIG. 4, 460a, 460b ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 – 7, 11 – 14, 17 – 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Fujiwara ( Pub. No. US 20200020699 A1 ), herein after Fujiwara.
Regarding Claim 4 (Original), Chang teaches the device as claimed in claim 1, on which this claim is dependent,
Chang does not explicitly teach:
further comprising a cut region between the gate regions of an adjacent pair of memory cells, wherein the cut region includes a trench formed in the substrate and a dielectric layer deposited in the trench.
However, Fujiwara teaches:
further comprising a cut region between the gate regions of an adjacent pair of memory cells, wherein the cut region includes a trench formed in the substrate and a dielectric layer deposited in the trench ( Fujiwara, FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206. CPODE layout pattern 206 extends in the second direction Y, and covers gate layout pattern 204c. In some embodiments, CPODE layout pattern 206 is useable to indicate that a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) of integrated circuit 300 (FIGS. 3A-3I) and 500 (FIG. 5) is removed, and a trench is formed and filled with an insulating portion 330 in the first well 301 (FIGS. 3A-3I) and the second well 302 (FIGS. 3A-3I); [0058], poly cut feature layout patterns 208a and 208b (collectively referred to as “set of cut feature layout patterns 208”). Set of poly cut feature layout patterns 208 extends in the first direction X ).
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206 … covers gate layout pattern 204c … a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) … is removed, and a trench is formed and filled with an insulating portion 330; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ a cut region between the gate regions of an adjacent pair of memory cells, wherein the cut region includes a trench formed in the substrate and a dielectric layer deposited in the trench ”. Doing so would use Fujiwara’s CPODE layout patent 206 as a similar solution of Chang’s MD vacancy location 460a and 460b, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 5 (Original), Chang and Fujiwara teach the device as claimed in claim 4, on which this claim is dependent, Chang further teaches:
wherein the cut region ( Chang, FIG. 4, 460a; [0034], MD vacancy location 460a ) and a source/drain contact ( Chang, FIG. 4, 430a ) connected to a floating source/drain terminal ( Chang, [0034], as the first terminal 203a of the antifuse transistor 202a and the first terminal 203b of the antifuse transistor 202b are floating terminals ) have substantially the same CPP ( Chang, FIG. 4, from 460a to 430a ) as the adjacent pair of gate regions ( Chang, FIG. 4, from 420a to 420b ) of a memory cell ( Chang, FIG. 4, 102a ).
Regarding Claim 6 (Original), Chang and Fujiwara teach the device as claimed in claim 4, on which this claim is dependent, Chang and Fujiwara further teach:
the cut region ( Chang, FIG. 4, 460a, 460b; [0034], MD vacancy location 460a and 460b ) surrounds an adjacent pair of memory cells ( Chang, FIG. 4, 102a, 102b ); and
the cut region ( Chang, FIG. 4, 460a, 460b; [0034], MD vacancy location 460a and 460b ) is at left ( Chang, FIG. 4, 460a ), right ( Chang, FIG. 4, 460b ), and top ( Fujiwara, FIG. 2A, 208; [0058] ) boundaries of the memory cells ( Chang, FIG. 4, 102a, 102b ).
Regarding Claim 7 (Original), Chang teaches the device as claimed in claim 1, on which this claim is dependent, Chang further teaches:
wherein the memory cell further includes:
a first source/drain contact ( Chang, FIG. 4, 430a ) connected to a source/drain region of a first transistor ( Chang, FIG. 4, 202a ) and a source/drain region of a second transistor ( Chang, FIG. 4, 204a );
a first gate region ( Chang, FIG. 4, 420a ) corresponding to a gate terminal of the first transistor ( Chang, FIG. 4, 202a ) and between the first source/drain contact ( Chang, FIG. 4, 430a ) and the cut region ( Chang, FIG. 4, 460a );
a second source/drain contact ( Chang, FIG. 4, 430b ) connected to a bit line ( Chang, FIG. 2, BL 112; FIG. 4, 430a, 430b, 430c; [0029], The OTP memory cells 102a and 102b share a bit line (not shown in FIG. 3 for simplicity) that receives a signal BL0; [0036], The MD strip 430b is connected to the MO strip 440a through an MD via (i.e., VD) 450a (collectively 450). As such, the MO strip 440a serves as the metal strip for the bit line signal BL0 ); and
a second gate region ( Chang, FIG. 4, 420b ) corresponding to a gate terminal of the second transistor ( Chang, FIG. 4, 204a ) and between the first ( Chang, FIG. 4, 430a ) and second ( Chang, FIG. 4, 430b ) source/drain contacts.
Chang does not explicitly teach:
a cut region including a trench formed in the substrate and a dielectric material deposited in the trench.
However, Fujiwara teaches:
a cut region including a trench formed in the substrate and a dielectric material deposited in the trench ( Fujiwara, FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206. CPODE layout pattern 206 extends in the second direction Y, and covers gate layout pattern 204c. In some embodiments, CPODE layout pattern 206 is useable to indicate that a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) of integrated circuit 300 (FIGS. 3A-3I) and 500 (FIG. 5) is removed, and a trench is formed and filled with an insulating portion 330 in the first well 301 (FIGS. 3A-3I) and the second well 302 (FIGS. 3A-3I); [0058], poly cut feature layout patterns 208a and 208b (collectively referred to as “set of cut feature layout patterns 208”). Set of poly cut feature layout patterns 208 extends in the first direction X ) .
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206 … covers gate layout pattern 204c … a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) … is removed, and a trench is formed and filled with an insulating portion 330; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ a cut region including a trench formed in the substrate and a dielectric material deposited in the trench ”. Doing so would use Fujiwara’s CPODE layout patent 206 as a similar solution of Chang’s MD vacancy location 460a and 460b, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 11 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent,
Chang does not explicitly teach:
further comprising a cut region that surrounds two or more transistors.
However, Fujiwara teaches:
further comprising a cut region that surrounds two or more transistors ( Fujiwara, FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206. CPODE layout pattern 206 extends in the second direction Y, and covers gate layout pattern 204c. In some embodiments, CPODE layout pattern 206 is useable to indicate that a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) of integrated circuit 300 (FIGS. 3A-3I) and 500 (FIG. 5) is removed, and a trench is formed and filled with an insulating portion 330 in the first well 301 (FIGS. 3A-3I) and the second well 302 (FIGS. 3A-3I); [0058], poly cut feature layout patterns 208a and 208b (collectively referred to as “set of cut feature layout patterns 208”). Set of poly cut feature layout patterns 208 extends in the first direction X ).
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206 … covers gate layout pattern 204c … a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) … is removed, and a trench is formed and filled with an insulating portion 330; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ further comprising a cut region that surrounds two or more transistors ”. Doing so would use Fujiwara’s “poly cut feature layout patterns 208a and 208b” and “CPODE layout patent 206” as a similar solution of Chang’s “MD vacancy location 460a and 460b”, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 12 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent,
Chang does not explicitly teach:
further comprising a cut region that divides the first diffusion region into halves.
However, Fujiwara teaches:
further comprising a cut region that divides the first diffusion region into halves ( Fujiwara, FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206; [0058], poly cut feature layout patterns 208a and 208b (collectively referred to as “set of cut feature layout patterns 208”). Set of poly cut feature layout patterns 208 extends in the first direction X ).
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ further comprising a cut region that divides the first diffusion region into halves ”. Doing so would use Fujiwara’s “poly cut feature layout patterns 208a and 208b” and “CPODE layout patent 206” as a similar solution of Chang’s “MD vacancy location 460a and 460b”, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 13 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent, Chang further teaches: further comprising:
a first cut region portion ( Chang, FIG. 4, 460a ) that defines a first edge of the first diffusion region;
a second cut region portion ( Chang, FIG. 4, 460b ) that abuts a second edge of the first diffusion region; and
Chang does not explicitly teach:
a third cut region portion interconnecting the first and second cut region portions.
However, Fujiwara teaches:
a third cut region portion ( Fujiwara, FIG. 2A, 208b ) interconnecting the first and second cut region portions ( Fujiwara, FIG. 2A, 206 ).
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ a third cut region portion interconnecting the first and second cut region portions ”. Doing so would use Fujiwara’s “poly cut feature layout patterns 208a and 208b” and “CPODE layout patent 206” as a similar solution of Chang’s “MD vacancy location 460a and 460b”, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 14 (Original), Chang teaches the device as claimed in claim 8, on which this claim is dependent, Chang further teaches: further comprising:
a second diffusion region ( Chang, FIG. 4, 410; [0031] ) formed in the substrate and spaced apart from the first diffusion region ( Chang, FIG. 4, 410a; [0031] ) in the second direction;
one or more source/drain contacts ( Chang, FIG. 4, 430a, 430b, 430c ) formed over the second diffusion region ( Chang, FIG. 4, 410; [0031] );
one or more gate regions ( Chang, FIG. 4, 420a, 420b, 420c, and 420d ) formed over the second diffusion region ( Chang, FIG. 4, 410; [0031] ); and
Chang does not explicitly teach:
cut region portions surrounding the one or more source/drain contacts and the one or more gate regions.
However, Fujiwara teaches:
cut region portions ( Fujiwara, FIG. 2A, 208b, 206 ) surrounding the one or more source/drain contacts and the one or more gate regions.
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ a third cut region portion interconnecting the first and second cut region portions ”. Doing so would use Fujiwara’s “poly cut feature layout patterns 208a and 208b” and “CPODE layout patent 206” as a similar solution of Chang’s “MD vacancy location 460a and 460b”, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 17 (Original), Chang teaches the method as claimed in claim 16, on which this claim is dependent,
Chang does not explicitly teach: further comprising:
etching a trench in the substrate through the diffusion region; and
filling the trench with a dielectric material to form a first cut region portion between the gate regions of an adjacent pair of memory cells.
However, Fujiwara teaches:
etching a trench ( Fujiwara, FIG. 2A, 206, 208; [0057] ) in the substrate through the diffusion region; and
filling the trench with a dielectric material ( Fujiwara, FIG. 2A, 206, 208; [0057], a trench is formed and filled with an insulating portion 330 ) to form a first cut region portion ( Fujiwara, FIG. 2A, 208; [0058], poly cut feature layout patterns 208a and 208b (collectively referred to as “set of cut feature layout patterns 208”). Set of poly cut feature layout patterns 208 extends in the first direction X ) between the gate regions of an adjacent pair of memory cells.
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206 … covers gate layout pattern 204c … a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) … is removed, and a trench is formed and filled with an insulating portion 330; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ etching a trench in the substrate through the diffusion region; and filling the trench with a dielectric material to form a first cut region portion between the gate regions of an adjacent pair of memory cells ”. Doing so would use Fujiwara’s “poly cut feature layout patterns 208a and 208b” and “CPODE layout patent 206” as a similar solution of Chang’s “MD vacancy location 460a and 460b”, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 18 (Original), Chang teaches the method as claimed in claim 15, on which this claim is dependent, Chang further teaches: further comprising:
connecting a first source/drain contact ( Chang, FIG. 4, 430a ) to a source/drain region of a first transistor ( Chang, FIG. 2, FIG. 4, 202a ) and a source/drain region of a second transistor ( Chang, FIG. 4, 204a );
depositing a gate material to form first gate region ( Chang, FIG. 4, 420a ) that corresponds to a gate terminal of the first transistor ( Chang, FIG. 2, FIG. 4, 202a ) and that is between the first source/drain contact ( Chang, FIG. 4, 430a ) and the cut region ( Chang, FIG. 4, 460a );
connecting a second source/drain contact( Chang, FIG. 4, 430b ) to a bit line ( Chang, FIG. 2, BL 112; FIG. 4, 430a, 430b, 430c; [0029], The OTP memory cells 102a and 102b share a bit line (not shown in FIG. 3 for simplicity) that receives a signal BL0; [0036], The MD strip 430b is connected to the MO strip 440a through an MD via (i.e., VD) 450a (collectively 450). As such, the MO strip 440a serves as the metal strip for the bit line signal BL0 ); and
depositing a gate material to form a second gate region ( Chang, FIG. 4, 420b ) that corresponds to a gate terminal of the second transistor ( Chang, FIG. 4, 204a ) and that is between the first ( Chang, FIG. 4, 430a ) and second ( Chang, FIG. 4, 430b ) source/drain contacts.
Chang does not explicitly teach:
forming a cut region by:
etching a trench in the substrate; and
depositing a dielectric material in the trench;
However, Fujiwara teaches:
forming a cut region ( Fujiwara, FIG. 2A, 208b, 206 ) by:
etching a trench ( Fujiwara, FIG. 2A, 206, 208; [0057] ) in the substrate; and
depositing a dielectric material ( Fujiwara, FIG. 2A, 206, 208; [0057], a trench is formed and filled with an insulating portion 330 ) in the trench;
Chang and Fujiwara are both considered to be analogous to the claimed invention because they are forming semiconductor memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang ( FIG. 4, 460a, 460b; [0034], The MD vacancy location 460a and the MD vacancy location 460b (collectively 460); [0035], There are no MD strips disposed at the MD vacancy locations 460a and 460b ) to incorporate the teachings of Fujiwara ( FIG. 2A, 206, 208; [0057], a continuous polysilicon on oxide diffusion (OD) edge (CPODE) layout pattern 206 … covers gate layout pattern 204c … a dummy gate structure (gate structure 304c manufactured by gate layout pattern 204c) … is removed, and a trench is formed and filled with an insulating portion 330; [0058], poly cut feature layout patterns 208a and 208b ), to implement “ forming a cut region by: etching a trench in the substrate; and depositing a dielectric material in the trench ”. Doing so would use Fujiwara’s CPODE layout patent 206 as a similar solution of Chang’s MD vacancy location 460a and 460b, and therefore to reduce the risk of a large leakage current ( Chang, [0016], A vacancy terminal is a source/drain terminal that does not have a source contact structure or a drain contact structure … As a result, the risk of having a short between the gate and vacancy terminal of the antifuse transistor is eliminated, therefore reducing the risk of a large leakage current ) and also have a higher density of memory cells ( Fujiwara, [0053], gate layout pattern 204c is useable to manufacture a dummy gate structure … At least the set of gate layout patterns 204 of layout design … have a contact poly pitch (CPP) of 3 … by having a CPP of 3, layout design … have a higher density than other approaches ).
Regarding Claim 20 (Original), Chang and Fujiwara teach the method as claimed in claim 17, on which this claim is dependent, Chang and Fujiwara further teach:
forming second and third cut region portions ( Chang, FIG. 4, 460a, 460b ) that respectively define opposite edges of the diffusion region ( Chang, FIG. 4, 410, 410a ); and
interconnecting ( Fujiwara, FIG. 2A, 208; [0057] ) the first, second, and third cut region portions ( Fujiwara, FIG. 2A, 206; [0057] ) with a fourth cut region portion ( Fujiwara, FIG. 2A, 208; [0057] ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
