DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 19 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (US 2007/0192565 A1).
Examiner relies on the entire teachings of the Hoshino reference for this rejection; the examiner advises the applicant to carefully consider the entire teachings of the Hoshino reference to better understand the examiner’s position and claimed interpretations applied to the claimed invention.
The Hoshino reference teaches functionally equivalent recitations of the claimed invention, when the examiner applies Broadest Reasonable Interpretation, as follows:
CLAIMS 1, 19 & 20
Hoshino REF. TEACHINGS
1.An embedded control circuit, comprising:
Fig 1-13 with accompanying description; the examiner relies more on the teachings of fig 9 with 13
a bus interface circuit for communicating with a host processor;
Figs 1, 9 & 13 with accompanying description; par 69, “external interface 140 posses and interface 143, and an external CPU 201 can be connected via the interface unit 143”; the examiner notes that the external CPU 201 is connected to a third bus 193 via 140
a processor;
Figs 1, 9 & 13 with accompanying description; par 76, “internal CPU 113 controls the processing…through the first bus 191…by selecting circuits 131-136”
one or more peripheral modules;
Figs 1, 9 & 13 with accompanying description; par 78, “the processing circuits 121-126 can be connected to the first bus 191 or to the second bus 192…”
a circuit system connected to the bus interface circuit;
Figs 1, 9 & 13 with accompanying description; all connections between (140) & (191/192)
a first bus connected between the one or more peripheral modules and the circuit system; and
Figs 1, 9 & 13 with accompanying description; par 78, “the first bus 191 or to the second bus 192 by switching connection of each corresponding circuits 131-136” & all connections between (140) & (191/192)
a second bus connected between the one or more peripheral modules and the processor;
Figs 1, 9 & 13 with accompanying description; par 78, “the first bus 191 or to the second bus 192 by switching connection of each corresponding circuits 131-136” & all connections between (140) & (191/192)
wherein the circuit system is configured to:
Figs 1, 9 & 13 with accompanying description; all connections between (140) & (191/192)
communicate with the host processor through the bus interface circuit, and access the one or more peripheral modules via the first bus according to a command from the host processor;
Figs 1, 9 & 13 with accompanying description; par 70, “the external CPU 201 via the interface unit 143, and the selecting 131-136 which select each connection of the plurality of processing circuits 121-126 to the first bus or to the second bus 192”
and the processor is configured to access the one or more peripheral modules via the second bus.
Figs 1, 9 & 13 with accompanying description; par 70, “the internal bus 191 connected to the internal CPU 113…via interface unit 143 and selecting circuits 131-136 which select each connection of the plurality of processing circuits 121-126 to the first bus”
19. A peripheral access method applied to an embedded control circuit, the embedded control circuit comprising a bus interface circuit, a processor, one or more peripheral modules, and a circuit system, wherein the peripheral access method comprises: communicating, by the circuit system, with a host processor through the bus interface circuit, and accessing the one or more peripheral modules via a first bus according to a command from the host processor, wherein the first bus is connected between the one or more peripheral modules and the circuit system; and accessing, by the processor, the one or more peripheral modules via a second bus, wherein the second bus is connected between the one or more peripheral modules and the processor.
The teachings of the claim 1 are similarly applied
20. An electronic device, comprising: an embedded control circuit and a host processor; wherein the embedded control circuit comprises: a bus interface circuit for communicating with the host processor; a processor; one or more peripheral modules; a circuit system connected to the bus interface circuit; a first bus connected between the one or more peripheral modules and the circuit system; and a second bus connected between the one or more peripheral modules and the processor; wherein the circuit system is configured to: communicate with the host processor through the bus interface circuit, and access the one or more peripheral modules via the first bus according to a command from the host processor; and the processor is configured to access the one or more peripheral modules via the second bus.
The teachings of the claim 1 are similarly applied
As for independent claims 1, 19 & 20, the examiner notes that the Hoshino reference does not expressly disclose or identically labels the claimed “peripheral modules”, but rather labels the functionally equivalent teachings of the claimed invention as “circuits” (121-126); however, the Hoshino reference teachings of the “circuits” performs/functions the functionally equivalent limitations of the claimed “peripheral modules”; therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the Hoshino reference for the detailed teachings and reasons discussed above.
Claims 2-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (US 2007/0192565 A1) in light/view of the well-known & commonly practiced teachings in the art of the claimed invention.
The teachings of the parent/independent claim 1 are similarly applied for the following rejection; furthermore, the examiner give official notice on the following well-known & commonly practiced in the art discussions/teachings.
The examiner relies on the entire teachings of the Hoshino reference for this rejection; the examiner advises the applicant to carefully consider the entire teachings of the Hoshino reference to better understand the examiner’s position and claimed interpretations applied to the claimed invention.
The Hoshino reference teaches functionally equivalent teachings of the claimed invention, when the examiner applies Broadest Reasonable Interpretation, as follows:
CLAIMS 2-18
Hoshino REF. TEACHINGS
2. The embedded control circuit according to claim 1, further comprising a third bus connected between the processor and the circuit system.
Figs 4 & 9 with accompanying description, see the “third bus” with accompanying description
3. The embedded control circuit according to claim 2, wherein the processor is configured to transmit interrupt information about the one or more peripheral modules to the circuit system via the third bus, and the circuit system is configured to transmit the interrupt information to the host processor through the bus interface circuit.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing interrupt control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
4. The embedded control circuit according to claim 2, wherein the processor is configured to configure, via the third bus, a permission for the circuit system to access the one or more peripheral modules.
Figs 1, 9 & 13 with accompanying description; obvious well-known variations of operations that are commonly practiced in the industry: such as the teachings of par 77, CPU 113 operates as a bus master, and among the processing circuits 121-126…the selecting circuits 131-136 operates as a bus slave”
5. The embedded control circuit according to claim 1, wherein the circuit system is configured to access the one or more peripheral modules based on preset permissions.
Figs 1, 9 & 13 with accompanying description; obvious well-known variations of operations that are commonly practiced in the industry: such as the teachings of par 77, CPU 113 operates as a bus master, and among the processing circuits 121-126…the selecting circuits 131-136 operates as a bus slave”
6. The embedded control circuit according to claim 1, further comprising an interrupt signal line connected between the processor and the circuit system.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing interrupt control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
7. The embedded control circuit according to claim 6, wherein the circuit system is configured to transmit an interrupt signal to the processor via the interrupt signal line.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing interrupt control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
8. The embedded control circuit according to claim 7, wherein the circuit system is configured to transmit the interrupt signal to the processor via the interrupt signal line under a condition that a register of one of the one or more peripheral modules that is accessed by the host processor is configured to prohibit access.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing interrupt control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
9. The embedded control circuit according to claim 1, wherein the circuit system is configured to: receive a write command from the host processor through the bus interface circuit and write, based on the write command, data into a register of one of the one or more peripheral modules that corresponds to the write command via the first bus; and/or receive a read command from the host processor through the bus interface circuit and read, based on the read command, data from a register of one of the one or more peripheral modules that corresponds to the read command via the first bus.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
10. The embedded control circuit according to claim 2, wherein the circuit system comprises: a receive circuit configured to receive a bus command sent by the bus interface circuit; a parse circuit configured to parse the received bus command to obtain a destination address; and a first controller configured to access a register of one of the one or more peripheral modules that corresponds to the destination address.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
11. The embedded control circuit according to claim 10, wherein under a condition that the bus command is a write command, the parse circuit further obtains target data; and wherein the first controller is configured to write the target data into the register of the peripheral module that corresponds to the destination address.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
12. The embedded control circuit according to claim 10, wherein the circuit system further comprises: a generation circuit configured to generate a bus command; and a transmit circuit configured to transmit the generated bus command to the bus interface circuit to cause the generated bus command to be received by the host processor.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
13. The embedded control circuit according to claim 12, wherein the first controller is further configured to: transmit data read from the destination address to the generation circuit to cause the generation circuit to generate the bus command corresponding to the data and cause the transmit circuit to transmit the generated bus command to the bus interface circuit.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
14. The embedded control circuit according to claim 12, wherein the circuit system further comprises a second controller configured to receive information sent by the processor via the third bus.
Obvious from the teachings of Figs 4 & 9 with accompanying description with “third bus” operations
15. The embedded control circuit according to claim 14, wherein the second controller is further configured to receive interrupt information sent by the processor via the third bus, and transmit the interrupt information to the generation circuit to cause the generation circuit to generate the bus command corresponding to the interrupt information and cause the transmit circuit to transmit the generated bus command to the bus interface circuit.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing interrupt control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
16. The embedded control circuit according to claim 14, wherein the circuit system further comprises a security control module connected to the first controller and to the second controller; the second controller is further configured to receive permission information sent by the processor via the third bus and write the permission information into the security control module; and the first controller is further configured to determine a permission to access the destination address based on the permission information in the security control module.
Obvious well-known variations of operations that are commonly practiced in the industry: such as utilizing security control which is commonly practiced in the industry; The examiner takes official notice on well-known utilizations of interrupt control
17. The embedded control circuit according to claim 1, wherein the bus interface circuit comprises one or more bus interfaces.
Figs 1, 9 & 13 with accompanying description; all connections between (140) & (191/192)
18. The embedded control circuit according to claim 1, wherein the circuit system comprises: a receive circuit configured to receive a bus command sent by the bus interface circuit; a parse circuit configured to parse the received bus command to obtain a destination address; and a first controller configured to access a register of one of the one or more peripheral modules that corresponds to the destination address.
Obvious from the teachings of Figs 1, 9 & 13 with accompanying description; par 72, “means of the register write access from each CPU, after preparing a setting register which sets up selection of the selecting circuit 131-136, and by preparing the setting path from the internal CPU 113 or the external CPU 201
As for the dependent claims 2-18, further add well-known & commonly practiced functional operations such as accessing operations performed between connected circuits of a computing system; however, the added functions or operations are, not only well-known but, commonly known practices in the art of accessing system; therefore, one having ordinary skill in the art can easily add such well-known functions for its obvious functional benefits for providing variety of well-known benefits. In other words, one having ordinary skill in the art can easily add functional features to the well-known system for performing any well-known desired application. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to come up with the claimed invention from the teachings of Hoshino reference in view of light of the well-known beneficial functional operation/application for the detailed reasons and teachings discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181