DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 8-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,133,432 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 8 of the current application and claim 1 of the 432’ patent share many of the same limitations, The following 432’ patent claim 1 limitations can be found in claims 1 and 8 of the current invention:
A display substrate, comprising:
a base substrate, comprising a first display region and a second display region, wherein the first display region is located at a periphery of the second display region;
the first display region comprises a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits,
the plurality of first pixel circuits are connected with the plurality of first light-emitting elements in one-to-one correspondence;
the second display region comprises a plurality of second light-emitting elements; the plurality of second pixel circuits are connected with the plurality of second light-emitting elements in one-to-one correspondence;
the third pixel circuit is a dummy pixel circuit;
a plurality of data lines, located on the base substrate and not passing through the second display region, wherein, the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines, respective first data lines are configured to be connected with the first pixel circuits, and respective second data lines are configured to be connected with at least the second pixel circuits;
wherein, in a direction perpendicular to the base substrate, part of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least part of the third pixel circuits overlapping with the second data lines are insulated from the second data lines.
Claim 8 limitation in a direction perpendicular to the base substrate, at least part of the dummy pixel circuits overlapping with the second data lines is insulated from the second data lines is nearly identical to the 432 patent claim 2 limitations.
Claim 9 of the current invention is found in claim 1 of the 432’ patent.
Claim 10 of the current invention is nearly identical to claim 3 of the 432’ patent.
Claim 11 of the current invention is nearly identical to claim 4 of the 432’ patent.
Claim 12 of the current invention is nearly identical to claim 5 of the 432’ patent.
Allowable Subject Matter
Claims 8-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. This is conditioned upon applicant overcoming the above 112 rejection as well as filing an eTerminal disclaimer against the above 432’ patent to overcome the double patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art, Kim et al. (US 20200117062 A1), Yang (US 20190305012 A1), Hwang et al. (US 20150109189 A1), An (US 20200176527 A1), and Yang (US 20220069047 A1), do not teach each and every limitation of claim 8 as disclosed.
Note applicant specification defines the following claim terms as follows:
First-type pixel circuit- per applicant specification [0028] means the pixel is connected to the data line.
Second-type pixel circuit- per applicant specification [0028] means the pixel is disconnected from the data line.
Dummy pixel – per [0061] means the pixel is disconnected from the light emitter.
Examiner has labeled applicant figure 3 below which shows the limitations disclosed in claim 3.
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Yang (US 20220069047) figures 3-4 and 16-17 provide the closest teaching to the limitations of claim 8, however, does not detail all the limitations of the claim. For example, Yang teaches first and second display regions such as DA1-DA3, a plurality of light emitting elements L1-L3, a plurality of pixel circuits C1-C3, and a plurality of data lines 11-113. Yang however does not teach all the connections as disclosed in claim 8.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20200117062 A1).
Regarding claims 1 and 20, Kim teaches a display apparatus comprising a display substrate (Figs. 1-4, Title, display device on a first substrate 110), comprising:
a base substrate (Figs. 1-4, a first substrate 110);
a plurality of pixel circuits, located on the base substrate (Figs. 1 and 4 show pixels PX on the first substrate 110. Fig. 13 shows PX pixel circuit);
a plurality of data lines (Figs. 1-5, [0058], See data lines 171a), located on the base substrate (Figs. 4-5, data lines 171a are located on first substrate 110),
wherein the base substrate comprises a first display region and a second display region (Fig. 1, see first pixel row PXR and second pixel row PXR of display area DA which make up first display region. Second display region is area outside of these two rows),
the plurality of pixel circuits comprises a plurality of first-type pixel circuits (Fig. 1, see pixels in first pixel row PXR) and a plurality of second- type pixel circuits (Fig. 1, see pixels in second pixel row PXR), the first type pixel circuits and the second type pixel circuits are both located in the first display region (Fig. 1, see first pixel row PXR and second pixel row PXR of display area DA which make up first display region);
the first-type pixel circuits are electrically connected with data lines overlapping therewith (Fig. 1, the pixel circuits PX in the first row are electrically connected with data line 171a overlapping therewith) and the second-type pixel circuits are insulated from data lines overlapping therewith (Fig. 1, [0066], “in each pixel column PXC, the pixels PX arranged in the second direction y may each be electrically connected to one of a pair of data lines 171a and 171b in an alternating sequence.” Examiner notes this teaching mean the pixel circuits PX in the second row PXR are insulated from data line 171a overlapping therewith).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200117062 A1), as applied to claim 1 above, and further in view of Yang et al. (US 20220069047 A1).
Regarding claim 3, Kim teaches at least part of the first-type pixel circuits are configured to drive a light-emitting element connected therewith to emit light ([0059]).
Kim does not teach the second-type pixel circuit is a first dummy pixel circuit.
Yang teaches a display substrate wherein a second-type pixel circuit is a first dummy pixel circuit (Fig. 17, [0127-0128] dummy pixel circuit Cud).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Kim with Yang such that the second pixels are dummy pixels as Yang teaches, “during the manufacturing process of the display panel, the problem of uneven exposure or etching caused by dramatic changes in the etching pattern (such as density changes) can be transferred to the dummy pixel circuit units CUd, thereby preventing uneven exposure or etching from affecting the brightness of the second light-emitting elements” (Yang, [0128]).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200117062 A1) in view of Yang et al. (US 20220069047 A1), as applied to claim 3 above, and further in view of Hwang et al. (US 20150109189 A1).
Regarding claim 4, Kim teaches the display substrate according to claim 3, wherein the first-type pixel circuits comprise a first pixel circuit and a second pixel circuit (Figs. 1-2, see First and second pixel circuits PX within first row of PXR);
the first pixel circuit overlaps with the light-emitting element connected therewith in a direction perpendicular to the base substrate ([0059] teaches each pixel circuit emits color and light therefore meaning a light-emitting element overlaps and is connected to the pixel circuit).
Kim and Yang do not teach the second pixel circuit does not overlap with the light-emitting element connected therewith in the direction perpendicular to the base substrate; and
the first-type pixel circuits further comprise a second dummy pixel circuit.
Hwang teaches a display substrate wherein first-type pixel circuits comprise a first pixel circuit and a second pixel circuit (Fig. 2, see emitting pixels EP and EPij);
the second pixel circuit does not overlap with the light-emitting element connected therewith in the direction perpendicular to the base substrate (See Fig. 2, [0070] wherein an emitting device E and a pixel circuit C do not overlap);
the first-type pixel circuits further comprise a second dummy pixel circuit (Fig. 2, see dummy pixel Dpi dummy pixel circuit DC).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Kim and Yang with Hwang to such that the second pixel circuit does not overlap with the light-emitting element as Hwang teaches an emitting element E may be coupled to a pixel circuit C via a separable wire 13 such that a defective pixel can be repaired (Hwang, [0005-0006]).
Regarding claim 5, Kim teaches wherein the second-type pixel circuits and part of the first-type pixel circuits are located in a same column (Fig. 1, see pixel PX in first row PXR and pixel PX in second row PXR which are in the same first column).
Hwang also teaches wherein the second-type pixel circuits and part of the first-type pixel circuits are located in a same column ([0071], “an emitting pixel EPij and a dummy pixel DPj that is positioned at the same column”).
Regarding claim 6, Kim teaches the second-type pixel circuits and the second pixel circuits are located in a same column (Fig. 1, see pixel PXR is second rows and fourth rows which are in a same column).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200117062 A1), as applied to claim 1 above, and further in view of An (US 20200176527 A1).
Regarding claim 7, Kim teaches the display substrate according to claim 1, wherein the pixel circuit comprises a data writing transistor (Fig. 13, [0115], see a first transistor Qa);
the data writing transistor comprises a first electrode, a second electrode, and a gate electrode (Fig. 13, a first transistor Qa comprises the claimed electrodes as shown in the figure).
Kim does not provide the layering details of the data writing transistor and therefore is not relied upon for teaching the remaining limitations.
An figures 2A-2B teach an insulating layer is provided between a film layer where the first electrode of the data writing transistor is located and a film layer where the data line is located (Fig. 2A shows insulating layer IL is provided between thin-film transistor (TFT) electrodes and signal line SGL. [0065] teaches SGL corresponds to a data line);
first electrodes of data writing transistors of the first-type pixel circuits are connected with the corresponding data line through a via hole located in the insulating layer (See fig. 2A which shows insulating layer between signal line SGL and pixel TFT electrodes along with fig. 7 which shows the data line DL is connected to pixel P switching transistor T2. These figures in combination teach a via hole must exist in the insulating layer to connect the signal line to the pixel TFT); and
first electrodes of data writing transistors of the second-type pixel circuits are insulated from the data line by the insulating layer (Fig. 2A shows insulating layer IL separates the electrodes of dummy transistor TFT’, which corresponds to data writing transistor of a second-type pixel circuit, from SGL which is a data line per [0065]).
It would have been obvious to one skilled in the art, before the effective filing date of the invention to modify Kim with An such that Hwang’s active pixels are connected to the data line and dummy pixels are insulated from the data line as An teaches his arrangement of dummy pixels between active pixels may protect the active pixels from electrostatic discharge (ESD) as “the dummy pixels Pd may serve as a buffer to prevent a large voltage due to ESD from being transmitted to the pixels P” (An, [0096]).
Response to Arguments
Applicant’s arguments with respect to claims 1-7 and 20 are directed towards the amended subject matter. As detailed in the rejection above, Kim teaches all the limitations as currently presented.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN P BRITTINGHAM whose telephone number is (571)270-7865. The examiner can normally be reached Monday-Thursday, 10 AM - 6 PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN P BRITTINGHAM/Examiner, Art Unit 2629
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