DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-10 still pending.
Claim 1 was amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The new ground(s) of rejection presented in this Office action is necessitated by Applicant's amendment.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by Erickson et al. US 12,132,387 (Erickson).
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Regarding claim 1, Erickson discloses an interleaved active neutral point clamped (ANPC) circuit (for example see Fig. 4) including N parallel bridge arms, wherein N is greater than 2 (for example see column 7, lines 25-33), the interleaved ANPC circuit comprising:
direct current (DC) terminals including a positive DC terminal (i.e., Vpv+) (Fig. 4) and a negative DC terminal (i.e., Vpv-) (Fig. 4); an alternating current (AC) terminal (i.e., AC output phase) (Fig. 4);
a first switching circuit (i.e., 311) (Fig. 4) connected between the positive DC terminal (i.e., Vpv+) (Fig. 4) and the negative DC terminal (i.e., Vpv-) (Fig. 4) and comprising a first switching transistor (i.e., 311) (Fig. 4), a second switching transistor (i.e., 314) (Fig. 4), a third switching transistor (i.e., 317) (Fig. 4), and a fourth switching transistor (i.e., 320) (Fig. 4) sequentially connected in series, series nodes of the first switching transistor (i.e., 311) (Fig. 4), the second switching transistor (i.e., 314) (Fig. 4), the third switching transistor (i.e., 317) (Fig. 4), and the fourth switching transistor (i.e., 320) (Fig. 4) being sequentially a first node (i.e., 111) (Fig. 4), a second node (i.e., 113) (Fig. 3), and a third node (i.e., 112) (Fig. 4), wherein the second node (i.e., 113) (Fig. 4) is connected to a neutral line;
and N parallel high-frequency switching circuits connected between the first node (i.e., 111) (Fig. 4) and the third node (i.e., 112) (Fig. 4), each of the N parallel high-frequency switching circuits (i.e., 331, 335) (Fig. 4) comprising a first high-frequency switching transistor (i.e., 331) (Fig. 4) and a second high-frequency switching transistor (i.e., 335) (Fig. 4) connected in series, wherein a phase difference between two adjacent high-frequency switching circuits among the N parallel high-frequency switching circuits is 2π/N.
Regarding claim 2, Erickson, as applied in linking claims, discloses frequencies of the first switching transistor (i.e., 311) (Fig. 4), the second switching transistor (i.e., 314) (Fig. 4), the third switching transistor (i.e., 317) (Fig. 4), and the fourth switching transistor (i.e., 320) (Fig. 4) are power frequencies.
Regarding claim 3, Erickson, as applied in linking claims, discloses the first switching transistor (i.e., 311) (Fig. 4), the second switching transistor (i.e., 314) (Fig. 4), the third switching transistor (i.e., 317) (Fig. 4), and the fourth switching transistor (i.e., 320) (Fig. 4) are IGBTs or MOSFETs.
Regarding claim 4, Erickson, as applied in linking claims, discloses the frequencies of the first high-frequency switching transistor (i.e., 331) (Fig. 4) and the second high-frequency switching transistor (i.e., 335) (Fig. 4) are greater than or equal to 1 kHz.
Regarding claim 5, Erickson, as applied in linking claims, discloses the first high-frequency switching transistor (i.e., 331) (Fig. 4) and the second high-frequency switching transistor (i.e., 335) (Fig. 4) are SiC or GaN MOSFETs.
Regarding claim 6, Erickson, as applied in linking claims, discloses the interleaved ANPC circuit comprising N LC filtering circuits (i.e., 334, 344, 353) (Fig. 4), a first terminal of each of the N LC filtering circuits is connected to a node between the first high-frequency switching transistor (i.e., 331) (Fig. 4) and second high-frequency switching transistor (i.e., 335) (Fig. 4) of a corresponding high-frequency switching circuit, and a second terminal of each of the N LC filtering circuits (i.e., 334, 344, 353) (Fig. 3) is connected to the AC terminal (i.e., Output) (Fig. 4).
Regarding claim 7, Erickson, as applied in linking claims, discloses the N LC filtering circuits (i.e., 334, 344, 353) (Fig. 4) share one capacitor (i.e., 353) (Fig. 4) or share a plurality of parallel capacitors.
Regarding claim 8, Erickson, as applied in linking claims, discloses the interleaved ANPC circuit, wherein a phase difference between first high-frequency switching transistors (i.e., 331, 335) (Fig. 4) of the two adjacent high-frequency switching circuits among the N parallel high-frequency switching circuits is 2π/N, and a phase difference between second high-frequency switching transistors (i.e., 341, 345) (Fig. 4) of the two adjacent high-frequency switching circuits among the N parallel high-frequency switching circuits is 2π/N.
Regarding claim 9, Erickson, as applied in linking claims, discloses the interleaved ANPC circuit is configured to perform DC-AC conversion or AC-DC conversion.
Regarding claim 10, Erickson, as applied in linking claims, discloses the first switching circuit (i.e., 311, 314, 317, 320) (Fig. 4) and the high-frequency switching circuits (i.e., 331, 335, 341, 345) (Fig. 4) are configured to perform the following operations:
during a positive half cycle, the first switching transistor (i.e., 311) (Fig. 4) and the third switching transistor (i.e., 317) (Fig. 4) are turned on, the second switching transistor (i.e., 314) (Fig. 4) and the fourth switching transistor (i.e., 320) (Fig. 4) are turned off, and the first high-frequency switching transistor (i.e., 331) (Fig. 4) and the second high-frequency switching transistor (i.e., 341) (Fig. 4) are alternately turned on;
and during a negative half cycle, the first switching transistor (i.e., 311) (Fig. 4) and the third switching transistor (i.e., 317) (Fig. 4) are turned off, the second switching transistor (i.e., 314) (Fig. 4) and the fourth switching transistor (i.e., 320) (Fig. 4) are turned on, and the first high-frequency switching transistor (i.e., 331) (Fig. 4) and the second high-frequency switching transistor (i.e., 341) (Fig. 4) are alternately turned on.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
For example see US Patent 9,960,708 – Figures 2 and Figure 3.
Also, Najjar et al. L.B., 2023, September. A high power density three-phase three-level hybrid igbt/sic interleaved active neutral point clamped voltage source converter. In 2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe) (pp. P-1). IEEE (Najjar), as applied in previous office action, only fail to teach N (parallel bridge arms) greater than 2, but Erickson (US 12,132,387) in the same field of endeavor discloses the use of more than 2 parallel bridge arms for introducing high-frequency pulse-width modulation into a plurality of ac output voltages.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YAHVEH COMAS TORRES/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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