Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim/s 1, 9-11, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pub. No. US 2023/0229357) in view of Bahirat (Pub. No. US 2024/0069722).
Claim 1, 9, 14, Lee teaches “a processing device comprising: a plurality of cores coupled to a memory device that stores data, wherein the plurality of cores are to perform operations comprising executing ([0040] In an embodiment, the CPU 121 and the computation engine 122 are illustrated as being separate function blocks, but an embodiment is not limited thereto. For example, each of the CPU 121 and the computation engine 122 may be implemented as an independent processor core. Alternatively, the CPU 121 and the computation engine 122 may be implemented as one processor core or may be implemented as a multi-core processor including a plurality of processor cores. [Fig. 1, 119] NVM device [0041] The FTL 123 may perform various maintenance operations for efficiently using the NVM device 119. For example, the maintenance operations may include an address mapping operation, a wear-leveling operation, a garbage collection operation, etc): a plurality of service applications that implement at least a portion of a flash translation layer (FTL) to direct operations to be performed by the memory device with reference to the data while tracking translations between a logical block address space to a physical address space ([0093] The FTL accelerator 123a may be a hardware circuit configured to automatize a function of the FTL 123, such as address mapping or block allocation. The FTL accelerator 123a may perform address mapping or block allocation, based on information provided from the NVMe engine 128b. For example, the FTL accelerator 123a may translate a logical address provided from the NVMe engine 128b into a physical address of the NVM device 119. Information about the translated physical address may be provided to the memory interface block 129.)”.
However, Lee may not explicitly teach the remaining limitations.
Bahirat teaches “an FTL service framework that comprises a plurality of application programming interfaces (APIs), wherein the plurality of APIs are configured to standardize communication between the plurality of service applications across the plurality of cores during runtime operation of the plurality of cores ([0102] FIG. 5 illustrates a system 500 that translates commands (e.g., specified by the NVMe specifications) into calls to a flash API using a lite flash translation layer (“FTL”) 508 implementation hosted by a DPU 504, in accordance with at least one embodiment. In the example illustrated, the system 500 includes a host CPU 502, the DPU 504, and one or more memory devices 510A-510E (e.g., SSDs). The memory device 510E may be implemented as a remote memory device and the memory devices 510A-510D may be implemented as local memory devices. The host CPU 502 may implement a kernel or application stack 503. The DPU 504 may implement an NVMe driver 506 and the lite FTL 508. In the example illustrated, the memory devices 510A-510E implement flash APIs 512A-512E, respectively, and flash management APIs 514A-514E, respectively. [0105] In at least one embodiment, the lite FTL 508 may be implemented as multiple components. For example, the lite FTL 508 may include a separate component implementing an NVMe-to-flash API convertor for each personality type (such as KV, OCP, ZNS, and/or the like) of the memory devices 510A-510E. In other examples, the NVMe-to-flash API converter may be implemented using at least one component that interfaces with multiple personality types of the memory devices 510A-510E (e.g., SSD). In at least one embodiment, components of the lite FTL 508 may be dynamically swapped or replaced with new components that support updated or different memory architectures.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Bahirat with the teachings of Lee in order to provide a system that teaches APIs. The motivation for applying Bahirat teaching with Lee teaching is to provide a system that allows for design choice. Lee, Bahirat are analogous art directed towards FTL based resource managemend. Together Lee, Bahirat teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Bahirat with the teachings of Lee by known methods and gained expected results.
Claim 10, the combination teaches the claim, wherein Bahirat teaches “the system of claim 9, wherein at least a first API of the plurality of APIs is configured to send a service request from a first service application to a second service application to request a particular action be performed by the second service application ([0098] In various examples, the software-defined flash API 412 allows common components (e.g., the common software stack 408) that are adapted for use with specific types of memory devices to use one or more of the physical memory device(s) 414 of the same or different types. The software-defined flash API 412 may, in some examples, translate an interface from one type of memory device to another. For example, the common software stack 408 that includes one or more applications in user space may access storage services via a set of common drivers 410 within the common storage API 409. The set of common drivers 410 may include file system and logical block device APIs (e.g., the APIs 312 and 314 illustrated in FIG. 3), as well as a set of APIs for accessing memory device of various types. The APIs for various memory device types, also referred to as an abstraction layer (e.g., the abstraction layer 316 illustrated in FIG. 3), may be implemented as a single library supporting multiple memory device types, or as multiple libraries. The abstraction layer translates the type-specific interface to the software-defined flash API 412, which converts a common set of commands into commands specific to the physical memory device. Therefore, the type of memory device interface provided to an application by the abstraction layer may be different than the actual type of the memory device present in one or more of the physical memory device(s) 414 accessed by the application.)”.
Rationale to claim 1 is applied here.
Claim 11, the combination teaches the claim, wherein Bahirat teaches “the system of claim 10, wherein the service request is a common service request selected from a group of service request types comprising at least two of: a work request notifying the second service application of the particular action ([0098] In various examples, the software-defined flash API 412 allows common components (e.g., the common software stack 408) that are adapted for use with specific types of memory devices to use one or more of the physical memory device(s) 414 of the same or different types. The software-defined flash API 412 may, in some examples, translate an interface from one type of memory device to another. For example, the common software stack 408 that includes one or more applications in user space may access storage services via a set of common drivers 410 within the common storage API 409. The set of common drivers 410 may include file system and logical block device APIs (e.g., the APIs 312 and 314 illustrated in FIG. 3), as well as a set of APIs for accessing memory device of various types. The APIs for various memory device types, also referred to as an abstraction layer (e.g., the abstraction layer 316 illustrated in FIG. 3), may be implemented as a single library supporting multiple memory device types, or as multiple libraries. The abstraction layer translates the type-specific interface to the software-defined flash API 412, which converts a common set of commands into commands specific to the physical memory device. Therefore, the type of memory device interface provided to an application by the abstraction layer may be different than the actual type of the memory device present in one or more of the physical memory device(s) 414 accessed by the application.); a synchronization request prompting the second service application to synchronize and flush data associated with the second service application; a suspension request prompting the second service application to suspend service; an activate request prompting the second service application to activate service; a reset request prompting the second service application to reset service; a persist request prompting the second service application to store internal data to a particular memory location ([0098] The abstraction layer translates the type-specific interface to the software-defined flash API 412, which converts a common set of commands into commands specific to the physical memory device. Therefore, the type of memory device interface provided to an application by the abstraction layer may be different than the actual type of the memory device present in one or more of the physical memory device(s) 414 accessed by the application.); a restore request prompting the second service application to restore service; or a response from a request prompting the second service application to transmit a response to a previously received service request.
Claim/s 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Park (Pub. No. US 2021/0064471).
Claim 2, the combination may not explicitly teach the limitation.
Park teaches “the processing device of claim 1, wherein the plurality of service applications and the FTL service framework are configured to be being implemented, without modification, on a different plurality of cores implementing a different FTL design architecture ([0089] Herein, the firmware may be referred to as a flash translation layer (FTL). An example of the FTL is later described in detail, referring to FIG. 3. According to an embodiment, the processor 134 may be implemented with a microprocessor or a central processing unit (CPU). [0131] According to an embodiment, the firmware loaded in the memory 144 may be shared by the plurality of cores 192, 194, 196, 198. The firmware may be copied or installed in a region allotted to each core 192, 194, 196, 198. In addition, according to an embodiment, the firmware can be divided into a plurality of modules, according to functional characteristics. Some modules of the firmware may individually and independently used by each of the cores 192, 194, 196, 198, and some modules may be shared by the cores 192, 194, 196, 198. In this case, a shared module may be loaded in a shared area of the memory 144. A non-shared module may be individually loaded at each region allotted to the corresponding core within the memory 144.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Park with the teachings of Lee, Bahirat in order to provide a system that teaches different architecture. The motivation for applying Park teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Park are analogous art directed towards FTL based resource management. Together Lee, Bahirat, Park teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Park with the teachings of Lee, Bahirat by known methods and gained expected results.
Claim/s 3, 5, 7, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Jayamohan (Pub. No. US 2012/0084777).
Claim 3, the combination may not explicitly teach the limitation.
Jayamohan teaches “the processing device of claim 1, wherein the plurality of APIs are respectively configured to: initialize a service directory, which is performed once per core for the plurality of cores; register a service execution set in the service directory; register each service application with the service execution set; and run the service applications as a group that comprises the service execution set ([0078] In process 700, features and associated feature properties of the processor cores are identified (act 702). These processor cores can be virtual cores or physical cores as discussed above, and the features and associated feature properties can be identified in different manners as discussed above. [0079] An operating system level scheduler schedules applications for execution on the processor cores (act 704). This scheduling can be determined based at least in part on the processor core features and associated feature properties identified in act 702, as discussed above. [0080] When a particular application is scheduled for execution, a user level scheduler of that particular application schedules threads of the application for execution on particular processor cores (act 706). This scheduling can be determined based at least in part on the processor core features and associated feature properties identified in act 702, as discussed above. [0025] Host operating system 102 includes a core feature tracking module 124 that identifies, for each physical core 106, the features that the physical core 106 supports. A feature of a physical core 106 refers to particular functionality that the physical core 106 supports. A physical core 106 supports a feature if the physical core 106 can execute types of instructions (e.g., understands operation codes (opcodes)) that provide that feature. The features that a physical core 106 supports can be identified in different manners, such as by particular functionality (e.g., a name or type of feature that includes multiple instruction types), by individual instruction types, and so forth.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Jayamohan with the teachings of Lee, Bahirat in order to provide a system that teaches initialization details. The motivation for applying Jayamohan teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Jayamohan are analogous art directed towards FTL based resource management. Together Lee, Bahirat, Jayamohan teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Jayamohan with the teachings of Lee, Bahirat by known methods and gained expected results.
Claim 5, the combination teaches the limitation, wherein Jayamohan teaches “the processing device of claim 3, wherein the service execution set comprises a plurality of applications of an event-driven type that are configured to execute in response to detecting an FTL-related event, and wherein the operations further comprise associating, with the service execution set, at least one of: a set of events, each of which is associated with a service registered with the service execution set, a set of events for services coordination ([0055] However, if there is another physical core that supports the instruction identified in act 504, then the virtual core that attempted to execute the identified instruction that cause the undefined opcode exception is scheduled for another physical core that supports the identified instruction (act 510). The virtual machine control module then indicates to the virtual core to attempt to execute the identified instruction again (act 512). As the virtual core is scheduled for a physical core that supports the instruction, this subsequent attempt to execute the identified instruction should not result in an undefined opcode exception. In one or more embodiments, the virtual core remains scheduled for the physical core that supports the instruction. The virtual core is thus provided a temporal affinity or "stickiness" to that physical core so that the virtual core remains scheduled for that physical core for an amount of time (e.g., until a particular amount of time elapses, until a particular event occurs such as another exception or another virtual core is scheduled for execution on that physical core, and so forth). Alternatively, after the identified instruction has been executed the virtual core can be re-scheduled for a different physical core (e.g., the physical core that the virtual core was scheduled for when the undefined opcode exception was received).), or a bitmask to indicate a trigger event bit value associated with each respective service application of the service execution set”.
Rationale to claim 3 is applied here.
Claim 7, the combination may not explicitly teach the limitation.
Jayamohan teaches “the processing device of claim 1, wherein the FTL service framework is to perform operations comprising: registering, with a unique identifier, each service application of the plurality of service applications to a particular core of the plurality of cores; and inserting each service application into a service directory that is capable of being queried ([0078] In process 700, features and associated feature properties of the processor cores are identified (act 702). These processor cores can be virtual cores or physical cores as discussed above, and the features and associated feature properties can be identified in different manners as discussed above. [0079] An operating system level scheduler schedules applications for execution on the processor cores (act 704). This scheduling can be determined based at least in part on the processor core features and associated feature properties identified in act 702, as discussed above. [0080] When a particular application is scheduled for execution, a user level scheduler of that particular application schedules threads of the application for execution on particular processor cores (act 706). This scheduling can be determined based at least in part on the processor core features and associated feature properties identified in act 702, as discussed above. [0025] Host operating system 102 includes a core feature tracking module 124 that identifies, for each physical core 106, the features that the physical core 106 supports. A feature of a physical core 106 refers to particular functionality that the physical core 106 supports. A physical core 106 supports a feature if the physical core 106 can execute types of instructions (e.g., understands operation codes (opcodes)) that provide that feature. The features that a physical core 106 supports can be identified in different manners, such as by particular functionality (e.g., a name or type of feature that includes multiple instruction types), by individual instruction types, and so forth.)”.
Rationale to claim 3 is applied here.
Claim 8, the combination teaches the claim, wherein Bahirat teaches “the processing device of claim 7, wherein the plurality of APIs are respectively configured to reference the service directory to perform at least one of: find a service application using a service identifie ([0102] FIG. 5 illustrates a system 500 that translates commands (e.g., specified by the NVMe specifications) into calls to a flash API using a lite flash translation layer (“FTL”) 508 implementation hosted by a DPU 504, in accordance with at least one embodiment. In the example illustrated, the system 500 includes a host CPU 502, the DPU 504, and one or more memory devices 510A-510E (e.g., SSDs). The memory device 510E may be implemented as a remote memory device and the memory devices 510A-510D may be implemented as local memory devices. The host CPU 502 may implement a kernel or application stack 503. The DPU 504 may implement an NVMe driver 506 and the lite FTL 508. In the example illustrated, the memory devices 510A-510E implement flash APIs 512A-512E, respectively, and flash management APIs 514A-514E, respectively. [0105] In at least one embodiment, the lite FTL 508 may be implemented as multiple components. For example, the lite FTL 508 may include a separate component implementing an NVMe-to-flash API convertor for each personality type (such as KV, OCP, ZNS, and/or the like) of the memory devices 510A-510E. In other examples, the NVMe-to-flash API converter may be implemented using at least one component that interfaces with multiple personality types of the memory devices 510A-510E (e.g., SSD). In at least one embodiment, components of the lite FTL 508 may be dynamically swapped or replaced with new components that support updated or different memory architectures.); send a service request to another service application to request a particular action be performed; clear a service request after having performed the particular action; retrieve a service request received from another service application; set a status of an associated service application; determine a status of the associated service application; query a status of another service application; register the associated service locally on a particular core; or register a proxy service application to communicate with a related service application running on a different core”.
Rationale to claim 1 is applied here.
Claim/s 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat, Jayamohan in further view of James (Pub. No. US 2008/0307208).
Claim 4, the combination may not explicitly teach the limitation.
James teaches “the processing device of claim 3, wherein the service execution set comprises a plurality of service applications of a polling type that are configured to execute continuously to completion except in response to event-based interruptions from event-driven service applications ([0022] Turning now to FIG. 7, the operation of the ASP 10 is described in accordance with one preferred embodiment. At the start, one of the contexts (any of contexts 20, 22 in FIG. 3 or contexts 1-4 in FIG. 5) will execute the instructions stored in the instruction RAM 24 directed to the operation of the application or task corresponding to that context (block 40). If a context switch instruction is not encountered during a polling or idle loop, or times of inactivity or while waiting for an event to occur during the operation of the application (block 42), the current context will continue to execute the instructions associated with the application corresponding to this context until completed (block 40). If, however, the current context does encounter a context switch instruction (block 42), the ASP 10 switches to the next context indicated in the context switch instruction (block 44). [0023] The next context (which becomes the current context) then begins executing instructions associated with the corresponding application (block 46) until a context switch instruction is encountered by this context during a polling or idle loop, or times of inactivity or while waiting for an event to occur during the operation of the application (block 48). This causes the ASP 10 to switch to the next context indicated in the context switch instruction (block 50), which may or may not be the same first context in which the ASP 10 began the initial operation.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of James with the teachings of Lee, Bahirat, Jayamohan in order to provide a system that teaches interruptions. The motivation for applying James teaching with Lee, Bahirat, Jayamohan teaching is to provide a system that allows for design choice. Lee, Bahirat, Jayamohan, James are analogous art directed resource management. Together Lee, Bahirat, Jayamohan, James teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of James with the teachings of Lee, Bahirat, Jayamohan by known methods and gained expected results.
Claim/s 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Veluswamy (Pub. No. US 2022/0229787).
Claim 6, the combination may not explicitly teach the limitation.
Veluswamy teaches “the processing device of claim 1, wherein the operations further comprise executing an out-of-bounds (OOB) message handler to handle OOB tasks related to auxiliary communication between the plurality of cores ([0060] In some embodiments, core allocator 564 may include data structures, functions, and/or interfaces configured to allocate new host connection requests to a particular processor core. For example, core allocator 564 may use connection type 562.1 determined by host request handler 562 to determine a connection type subset of core pool 542 and select a particular processor core within that subset to receive the host connection. In some embodiments, core allocator 564 may use a core ratio 564.1 to divide core pool 542 into connection type subsets, such as an RDMA connection subset and a TCP/IP connection subset. For example, core ratio 564.1 may be read from configuration data 520.2 and provide a user configurable allocation between cores assigned to RDMA connections and cores assigned to TCP/IP connections)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Veluswamy with the teachings of Lee, Bahirat in order to provide a system that teaches OOB handler. The motivation for applying Veluswamy teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Veluswamy are analogous art directed towards resource management. Together Lee, Bahirat, Veluswamy teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Veluswamy with the teachings of Lee, Bahirat by known methods and gained expected results.
Claim/s 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Jaladanki (Pat. No. US 9,122,599).
Claim 12, the combination may not explicitly teach the limitation.
Jaladanki teaches “the system of claim 9, wherein the operations further comprise maintaining, in the memory device, one or more doublewords of bits indicating one or more statuses associated with each service application of the plurality of service applications, wherein a first subset of the one or more doublewords are predefined and a second subset of the one or more doublewords are service-specific statuses ([Col. 11, Lines 3-16] (58) At block 908, upon receipt of the response such as GET-RESPONSE PDU, the enhanced diagnostic code is decoded in accordance with enhanced diagnostic information stored in a database. In one embodiment, module ID, sub-module ID, and application specific error code are identified in response to the enhanced diagnostic code in the database. The 32-bit error status bits are identified in a GET-RESPONSE formatted in SNMP PDU. Note that the first six (6) bits of the 32-bit error status bits indicate the module ID and the next six (6) bits of the 32-bit error status indicate the sub-module ID. The process is further able to locate twelve (12) bits following the sub-module ID in the 32-bit error status bits as application specific error code and the last five (5) bits of the 32-bit error status bits as a standard SNMP error code.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Jaladanki with the teachings of Lee, Bahirat in order to provide a system that teaches status bits. The motivation for applying Jaladanki teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Jaladanki are analogous art directed towards resource management. Together Lee, Bahirat, Jaladanki teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Jaladanki with the teachings of Lee, Bahirat by known methods and gained expected results.
Claim/s 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Fan (Pub. No. US 2020/0004692).
Claim 15, the combination may not explicitly teach the limitation.
Fan teaches “the method of claim 14, further comprising scheduling a service application of the plurality of service applications to run according to one of the following states based on priority of control: a disabled state in which the service application is not scheduled to run; a first priority state in which service application is scheduled to run in cyclical fashion with priority normalized to other service applications; and a second priority state, which has a higher priority than the first priority state, in which the service application is scheduled to run at a higher frequency than service applications in the first priority state ([0090] The architecture in difference between the GPU and the CPU leads to the different access memory characteristics of the two, applications running on the CPU have more sensitive cache requirements than applications running on the GPU. Based on this, in the embodiments, the cache priority of the second data accessed by the second application running on the GPU includes the highest cache priority, so that the second data accessed by the second application running on the CPU has a longer life cycle and a higher priority than the first data accessed by the first application running on the GPU. Thus, the second application running on the CPU can relatively acquire more space of the shared cache.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Fan with the teachings of Lee, Bahirat in order to provide a system that teaches priority-based scheduling. The motivation for applying Fan teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Fan are analogous art directed towards resource management. Together Lee, Bahirat, Fan teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Fan with the teachings of Lee, Bahirat by known methods and gained expected results.
Claim/s 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Bahirat in further view of Sandstrom (Pub. No. US 2023/0267008).
Claim 16, the combination may not explicitly teach the limitation.
Sandstrom teaches “the method of claim 14, further comprising: registering, with a unique identifier, each service application of the plurality of service applications to a particular core of the plurality of cores; reporting, via updates to state bits stored in the memory device that provide a common status, a service state for each service application ([Table 6] Instance ID Core type (within the (e.g., 0 denotes CPU, application 1 denotes DSP, of 2 denotes GPU, 3 . . . 15 Core ID Application column to denotes an ASP for a index ID the left) particular function, etc.) 0 P 0 0 1 B 0 0 2 B 8 2 . . . . . . . . . . . . 14 F 1 5 15 N 1 1); and for each service application, at least one of: updating, directly after the registering, the state bits to reflect a pre-initialization state; updating the state bits to reflect an initialization state; in response to the service application having no on-going data processing, updating the state bits to reflect an idle state; or in response to the service application undergoing data processing, updating the state bits to reflect an active state ([0187] The input data receive (RX) logic writes per each app the intra-app instance priority list per 4 to controller 540, to be used as an input for the active app-instance selection sub-process, which produces per-app listings of selected app-instances, along with their corresponding target core types where applicable. Based at least on the app specific lists of selected app-instances, the core to app-instance assignment algorithm produces a core ID# indexed array indexed with the app and instance IDs, and provides as its contents the assigned processing core ID (if any) for the app-instance with ID equal to the index of the given entry, per Tbl. 5 below:)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Sandstrom with the teachings of Lee, Bahirat in order to provide a system that teaches status tracking. The motivation for applying Sandstrom teaching with Lee, Bahirat teaching is to provide a system that allows for design choice. Lee, Bahirat, Sandstrom are analogous art directed towards resource management. Together Lee, Bahirat, Sandstrom teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Sandstrom with the teachings of Lee, Bahirat by known methods and gained expected results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WYNUEL S AQUINO whose telephone number is (571)272-7478. The examiner can normally be reached 9AM-5PM EST M-F.
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/WYNUEL S AQUINO/Primary Examiner, Art Unit 2199
