DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230108810 A1 (Choi), in view of US 20030201834 A1 (Pehlke) and in further view of US 20110043956 A1 (Su) and US 20240007057 A1 (Peng).
Regarding Claims 1, 7 and 14:
An apparatus for signal amplification, comprising: an amplifier; an over-current detection circuit coupled to the amplifier and configured to detect an over-current condition associated with the amplifier; and a latch having an input coupled to an output of the over-current detection circuit and configured to adjust an amplification gain to an adjusted amplification gain level for an input signal based on the over-current condition, wherein the amplification gain is maintained at the adjusted amplification gain level until occurrence of an amplifier gain event, wherein the amplifier is configured to amplify the input signal based on the adjusted amplification gain level (Choi: Fig. 2 and par. 45-52, a PA with a overdrive, i.e., over-current, detection and adjust (e.g., reducing) net bias current to the PA 11 through transconductance block 14, which in turn reduces the gain and hence output power of the power amplifier 11; the gain reduction can be removed through an edge-triggered block when the overdrive condition is no longer detected (i.e., “an amplifier gain event) as further detailed in Figs. 3-6 and corresponding descriptions).
Choi does not teach explicitly on adjusting bias/gain and maintaining it in a held state until a periodic transmit event occurs. However, Pehlke teaches (Pehlke: Fis. 7A-B and par. 48-50, “…the bias controller 52 to calibrate or otherwise adjust the bias voltage V.sub.BIAS to the level required to hit the target quiescent current level for the power amplifier circuit 60, and then lock and hold that adjusted bias voltage into and through one or more subsequent transmit bursts”, where “lock and hold” implies a latch operation; par. 7, “the bias controller transitions from its first state to its second state, at which point it locks or otherwise holds the adjusted level of bias voltage irrespective of any changes in the supply current into the power amplifier circuit.”; and furthermore Su teaches a hardware scheme to use latch for over-current detector to hold the gain status e.g. Su: Fig. 4 and par. 38-41, “…anti-toggling control circuit 380 includes M-1 D-type latches 480b through 480m, M-1 OR gates 482b through 482m, an inverter 484, and a delay circuit 486. Inverter 484 receives and inverts the B1 signal from comparator 470a. Delay circuit 486 receives and delays the B1 signal and provides a delayed B1 signal (B1d). Delay circuit 486 may be implemented with an even number of inverters coupled in series. OR gates 482b through 482m receive the same output signal from inverter 484 at one input and further receive the B2 through BM signals from comparators 470b through 470m, respectively, at the other input. Latches 480b through 480m receive the same delayed B1 signal from delay circuit 486 at a data (D) input and further receive X2 through XM signals from OR gates 482b through 482m…”)
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Choi with adjusting bias/gain and maintaining it in a held state until a periodic transmit event occurs as further taught by Pehlke and Su. The advantage of doing so is to enable the control of PA bias for accurate control of amplifier operation (Pehlke: Background]), and improve protection loop variations to avoid stability issue (Su: par. 32).
Choi does not teach explicitly on using an input attenuation network to adjust PA gain. However, Peng teaches (Peng: Fig. 2, a gain adjustable PA that uses overcurrent detection and protection; Fig. 5, the adjustment is through the attenuation network 503; Fig. 7, through input impedance adjustment).
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Choi with using an input attenuation network to adjust PA gain as further taught by Peng. The advantage of doing so is provide an overcurrent protection circuit and overvoltage protection circuit for a power amplifier may reduce a gain of the power amplifier or cut off the power amplifier, by reducing or closing a bias current of the power amplifier after protection is enabled (Peng: Background).
Regarding Claims 2 and 9, Choi as modified further teaches:
The method of claim 1, further comprising receiving an amplifier gain event signal indicating the occurrence of the amplifier gain event (Choi: par. 50, using edge-trigger block).
Regarding Claims 3, 10 and 16, Choi as modified further teaches:
The method of claim 2, wherein the amplifier gain event signal is a periodic signal (Pehlke: e.g., Fig. 7B and par. 48-50, “In GSM, transmit bursts consist of a burst start where the transmit power is ramped up to a defined level; followed by a modulation period, and then terminated by a ramp end”, where a transmit burst is the processing of a periodic new packet for transmission in digital communication networks like GSM).
Regarding Claims 4, 11 and 17 Choi as modified further teaches:
The method of claim 1, wherein the amplifier gain event is associated with processing of a new packet for transmission (Pehlke: e.g., Fig. 7B and par. 48-50, “In GSM, transmit bursts consist of a burst start where the transmit power is ramped up to a defined level; followed by a modulation period, and then terminated by a ramp end”, where a transmit burst is the processing of a periodic new packet for transmission in digital communication networks like GSM).
Regarding Claims 5, 12 and 18, Choi as modified further teaches:
The method of claim 1, wherein adjusting the amplification gain comprises adjusting a level of attenuation associated with an attenuator coupled to an input of the amplifier (Peng: Figs. 5 and 7; Su: Figs. 3, 6-7 and par. 55, “…a protection circuit may vary the gain of VGA 136, the gain of a digital multiplier within data processor 110, and/or the gain of other circuits in a transmit path to vary the RFout signal level”, where DA 342 is in the input path of PA).
Regarding Claims 6, 13 and 19, Choi as modified further teaches:
The method of claim 1, wherein adjusting the amplification gain comprises adjusting a bias current for the amplifier (Choi: Fig. 2, the transconductance block 14 reduces net bias current to the PA 11).
Regarding Claims 8 and 15, Choi as modified further teaches:
The apparatus of claim 7, further comprising a multiplexer configured to receive a first amplification gain code and a second amplification gain code, wherein an output of the latch is coupled to a select input of the multiplexer, and wherein an output of the multiplexer is coupled to: a current digital-to-analog converter (IDAC) having an output coupled to a bias current input of the amplifier; or a control input of an attenuator coupled to an input of the amplifier (Choi: Fig. 2 and par. 45-52, “A digital-to-analogue converter (DAC) 12 provides current to bias the power amplifier 11. When the capacitor is charged by excess current indicating an overdrive condition, the transconductance block 14 is driven by voltage over the capacitor 18 which acts to reduce or cancel the bias current from the DAC 12”, where DAC 12 provides the first amplification gain code (normal bias level), the transconductance block 14 driven by the capacitor voltage effectively applies the second gain code (reduced level), and edge trigger block (latch output) controls which state, normal or clamped, is applied (functioning as the multiplexer select; Su: Figs. 4-5 and par. 46-50, “The C2 through CM signals are indicative of the desired gain for driver amplifier 342 and are given in a first digital format. Thermal-to-binary encoder 390 receives the C2 through CM signals and generates D2 through DM signals indicative of the desired gain and given in a second digital format used for driver amplifier 342. The D2 through DM signals may correspond to gains G2 through GM, respectively. At most one of the D2 through DM signals may be set to logic high to select the corresponding gain”).
Regarding Claim 20, Choi as modified further teaches:
The apparatus of claim 14, wherein the latch comprises: a flip-flop having a clock input forming the first input of the latch and a reset input forming the second input of the latch; and an OR gate having a first input coupled to an output of the flip-flop, a second input coupled to the clock input of the flip-flop, and an output forming the output of the latch (Su: e.g., par. 41, “In the exemplary design shown in FIG. 4, anti-toggling control circuit 380 includes M-1 D-type latches 480b through 480m, M-1 OR gates 482b through 482m, an inverter 484, and a delay circuit 486… Latches 480b through 480m receive the same delayed B1 signal from delay circuit 486 at a data (D) input and further receive X2 through XM signals from OR gates 482b through 482m, respectively, at a clock input“; par. 46, “The input of each latch 480 is passed to its output only when a trigger signal from the corresponding OR gate 482 transitions to logic high”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm.
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/ZHITONG CHEN/
Primary Examiner, Art Unit 2649
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