DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 08/27/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8-11 & 18-20 is/are rejected under 35 U.S.C. 102a(1) as being by anticipated by Liikanen et al (US10446241).
Regarding claim 1, Liikanen discloses a memory controller(FIG 1; 100 comprising 106), comprising: a data buffer(132); and a control circuit coupled to the data buffer(130 coupled to 132), and wherein the control circuit is configured to: control a memory device to perform a read operation with a first read voltage corresponding to a first data state of a memory cell(FIG 2; 130 coupled to the memory 102 and performing a read operation using read request 230, 232 for performing 1st read level operation of 122) ; obtain a first number of memory cells with a threshold voltage being less than or equal to the first read voltage, and obtain a second number of memory cells with a threshold voltage being greater than the first read voltage(FIG 4D-4E; col 11, line 50 to col 12, line 4; discloses 106 sending signals to 110, that determine a number of memory cells with the memory regions e.g., output a specified data states current above a threshold value and below the threshold value), determine a difference between the second number and the first number(FIG 4D-4E; discloses e.g., VL2 read count and VL1 read count, and determining a count difference); and acquire a voltage offset value from a mapping table according to the difference(FIG 4D-4E; discloses acquiring a voltage difference offset value from table according to the difference, e.g., VL2 and VL1 count difference 52 is mapped on figure 4E).
Regarding claim 8, Liikanen discloses wherein the mapping table includes a second mapping table which includes a second interval of values and voltage offset values corresponding to the second interval of values(FIG 4D-4D; Vl1 and VA); and the memory controller is configured to: in response to the difference being within the second interval of values, acquire the voltage offset value corresponding to the second interval of values according to the second mapping table(FG 4D-4E; delta difference value between VL1 and Va 41).
Regarding claim 9, Liikanen discloses wherein the memory controller is configured to: enable a single level read operation mode, and control the memory device to perform a single level read operation with the first read voltage (FIG 1-2; 106 requesting read request, reading data return and performing 1st level).
Regarding claim 10, Liikanen discloses wherein the memory controller is further configured to: sum the first read voltage and the voltage offset value to obtain a second read voltage (FIG 5A; col 16, lines 48-67 discloses updating stored calibration value e.g., first read voltage by summing the value with the average total read level offset value to obtain an updated calibration value e.g., second value).
Regarding claim 11, Liikanen discloses a memory system, comprising: a memory device including a plurality of memory cells(FIG 1; 100 comprising 102 , comprising 122 memory cells), each of the plurality of memory cells being configured to store one of a plurality of data states(122 storing data).; and a memory controller coupled with the memory device and configured to(106): control the memory device to perform a read operation with a first read voltage corresponding to a first data state of the plurality of data states(FIG 2; 130 coupled to the memory 102 and performing a read operation using read request 230, 232 for performing 1st read level operation of first MC of 122); obtain the first number of memory cells with a threshold voltage being less than or equal to the first read voltage, and obtain a second number of memory cells with a threshold voltage being greater than the first read voltage(FIG 4D-4E; col 11, line 50 to col 12, line 4; discloses 106 sending signals to 110, that determine a number of memory cells with the memory regions e.g., output a specified data states current above a threshold value and below the threshold value); determine a difference between the second number and a first number; and acquire a voltage offset value from a mapping table according to the difference(FIG 4D-4E; discloses acquiring a voltage difference offset value from table according to the difference, e.g., VL2 and VL1 count difference 52 is mapped on figure 4E).
Regarding claim 18, Liikanen discloses wherein the mapping table includes a second mapping table which includes a second interval of values and voltage offset values corresponding to the second interval of values s(FIG 4D-4D; Vl1 and VA); and the memory controller is configured to: in response to the difference being within the second interval of values, acquire the voltage offset value corresponding to the second interval of values according to the second mapping table(FG 4D-4E; delta difference value between VL1 and Va 41).
Regarding claim 19, Liikanen discloses wherein the memory controller is further configured to: send a first operation command to the memory device; and the memory device is configured to: enable a single level read operation mode in response to the first operation command (FIG 1-2; 106 requesting read request command, reading data return and performing 1st level based on the read request command).
Regarding claim 20, Liikanen discloses a method for controlling a memory system(FIG 1-2 method for controlling 100), comprising: performing a read operation with a first read voltage corresponding to a first data state of a memory cell FIG 2; 130 coupled to the memory 102 and performing a read operation using read request 230, 232 for performing 1st read level operation of first cell of 122); obtaining a first number of memory cells with a threshold voltage being less than or equal to the first read voltage, and obtaining a second number of memory cells with a threshold voltage being greater than the first read voltage FIG 4D-4E; col 11, line 50 to col 12, line 4; discloses 106 sending signals to 110, that determine a number of memory cells with the memory regions e.g., output a specified data states current above a threshold value and below the threshold value); determining a difference between the second number and the first number; and acquiring a voltage offset value from a mapping table according to the difference(FIG 4D-4E; discloses acquiring a voltage difference offset value from table according to the difference, e.g., VL2 and VL1 count difference 52 is mapped on figure 4E).
Allowable Subject Matter
Claims 2-7 & 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Senoo et al (US20210366561 FIG 4A; discloses reading voltage generating unit 158, offset voltage determining unit 156, comparing unit 154, and current detecting unit 152, wherein unit 156 determined offset voltage of two values Vofs1 and Vofs2).
Tanzawa et al (US20120182510 FIG 2; [0050] discloses Vread 1 being applied to targeted memory cells to determine which of the target memory cells have Vt greater than or equal to Vread1).
Wang et al (US7729165 FIG 3; discloses having level voltages and verification, stepped gate voltage read being fed into SA, being compared with values of Irefe, Vref-deltaV, and Vref+deltaV).
Kang et al (US8023323 FIG 6; S110, S120, S130, S140, S150, S172).
Choi et al (US20230317201 FIG 3-4; discloses Step 302, 304 and 306).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/ Primary Examiner, Art Unit 2827
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