DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 08/03/2026.
Claim Objections
Claim 4 is objected to because of the following informalities: Claim 4, first line recites “the modulated signals”, which should be – the first and second modulated signals – because in this way were previously presented these terms in the claim.
Appropriate correction is required.
Claim 6 is objected to because of the following informalities: Claim 6, line 5 recites “the modulated signals”, which should be – the first modulated signals – because in this way were previously presented these terms in the claim; Claim 6, line 7 recites “the modulated signals”, which should be – the second modulated signals – because in this way were previously presented these terms in the claim.
Appropriate correction is required.
Claim 7 is objected to because of the following informalities: Claim 7, lines 5-6 recites “the modulated signals”, which should be – the first and second modulated signals – because in this way were previously presented these terms in the claim.
Appropriate correction is required.
Claim 8 is objected to because of the following informalities: Claim 8, line 6 recites “an on-resistance of of”, which appears a typographical error of – an on-resistance of –.
Appropriate correction is required.
Claim 13 is objected to because of the following informalities: Claim 13, lines 5 and 8 recite “the power converter”, which should be -- the power converter circuit – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 16 is objected to because of the following informalities: the claims status of Claim 16 is (Currently Amended) and should be (Canceled) because all the claim limitations were canceled.
Appropriate correction is required.
Claim 18 is objected to because of the following informalities: Claim 18, first line recites “the modulated signals”, which should be – the first and second modulated signals – because in this way were previously presented these terms in the claim.
Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 19, line 3 recites “the modulated signals”, which should be – the first and second modulated signals – because in this way were previously presented these terms in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-15 and 18-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tang et al. (US 2023/0104049), hereinafter Tang.
Regarding claim 13, Tang discloses (see figures 1-14) a method (figure 3) comprising: receiving a feedback signal (figures 3 and 7, part feedback signal input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) from a power converter circuit (figure 3, part power converter circuit at 11) having a configurable number of output voltage levels (figures 10 and 14, parts Two-level working mode and Three-level working mode) (paragraph [0117]-[0122]; he MCU is switched between the three-level working mode and the two-level working mode); responsive to the feedback signal (figures 3 and 7, part feedback signal input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) being above a threshold (figure 10, part feedback signal input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit; being above a threshold at left side of flow chart), providing first modulated signals (figures 3 and 7, part first modulated signals at control outputs from 113 and 114) to switches (figure 3, parts S1_A-C, S2_A-C, S3_A-C and S4_A-C) of the power converter (figure 3, part power converter circuit at 11) to cause the power converter circuit (figure 3, part power converter circuit at 11) to provide a voltage that switches between two levels (figures 10 and 14, part Two-level working mode) (paragraph [0117]-[0122]; the MCU enters a two-level working mode); and responsive to the feedback signal (figures 3 and 7, part feedback signal input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) being below the threshold (figure 10, part feedback signal input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit; being below the threshold at left side of flow chart), providing second modulated signals (figures 3 and 7, part second modulated signals at control outputs from 113 and 114) to the switches of the power converter (figure 3, parts S1_A-C, S2_A-C, S3_A-C and S4_A-C) to cause the power converter circuit (figure 3, part power converter circuit at 11) to provide a voltage that switches among more than two levels (figures 10 and 14, part Three-level working mode) (paragraph [0117]-[0122]; the MCU enters a three-level working mode).
Regarding claim 14, Tang discloses everything claimed as applied above (see claim 13). Further, Tang discloses (see figures 1-14) the feedback signal (figures 3 and 7, part feedback signal to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) indicates an amount of current being drawn at a switch terminal of the power converter circuit (figure 3, part S1_A; lower switch terminal; through feedback input to 112 of the current output) (paragraph [0091]; a T-type three-phase full-bridge three-level inverter circuit, a switching transistor in a horizontal bridge circuit is controlled based on torque of a motor, a current output by an output terminal, a temperature of the switching transistor in the horizontal bridge circuit, and a terminal voltage of the switching transistor in the horizontal bridge circuit).
Regarding claim 15, Tang discloses everything claimed as applied above (see claim 13). Further, Tang discloses (see figures 1-14) the feedback signal (figures 3 and 7, part feedback signal to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) indicates a temperature (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit) of a subset of the switches that are coupled between a switch terminal and a power output (figure 3, parts S3_A and S2_A) of the power converter circuit (figure 3, part power converter circuit at 11) (paragraph [0091]; a T-type three-phase full-bridge three-level inverter circuit, a switching transistor in a horizontal bridge circuit is controlled based on torque of a motor, a current output by an output terminal, a temperature of the switching transistor in the horizontal bridge circuit, and a terminal voltage of the switching transistor in the horizontal bridge circuit).
Regarding claim 18, Tang discloses everything claimed as applied above (see claim 13). Further, Tang discloses (see figures 1-14) the modulated signals (figures 3 and 7, part modulated signals at control outputs from 113 and 114) are at pulse width modulation signals (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13).
Regarding claim 19, Tang discloses everything claimed as applied above (see claim 13). Further, Tang discloses (see figures 1-14) accessing a memory component (figures 3 and 7, part memory component inside of 112) to determine the modulated signals (figures 3 and 7, part modulated signals at control outputs from 113 and 114) based on the feedback signal (figures 3 and 7, part feedback signal to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) (paragraph [0092]; The MCU 11 obtains torque of a motor or a current output by an output terminal of the MCU 11, converts one of the torque and the current (for example, converts one of the torque and the current by looking up a table) into a Q-axis current Iq and a D-axis current Id of the motor, obtains a corresponding Q-axis voltage Uq and a corresponding D-axis voltage Ud, performs further calculation to obtain a comparison value of a PWM control signal, calculates a duty cycle, controls, based on the duty cycle, a switching transistor to be conducted and cut off, converts a direct current output by a direct current power supply 12 into an alternating current, supplies power to a motor 13, and controls a voltage and a current of an output alternating current, to control a rotational speed of the motor).
Regarding claim 20, Tang discloses everything claimed as applied above (see claim 19). Further, Tang discloses (see figures 1-14) the memory component (figures 3 and 7, part memory component inside of 112) is a lookup table (LUT) (figures 3 and 7, part LUT at memory component inside of 112) (paragraph [0092]; looking up a table).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 11, 12, 17, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 2023/0104049), hereinafter Tang, in view of Hart et al. (US 2026/0261216), hereinafter Hart.
Regarding claim 1, Tang discloses (see figures 1-14) an apparatus (figure 3) comprising: a power converter circuit (figure 3, part power converter circuit at 11) including: a first switch (figure 3, part S1_A) coupled between a power input (figure 3, part S1_A; upper power input) and a switch terminal (figure 3, part S1_A; lower switch terminal), and a second switch (figure 3, part S4_A) coupled between the switch terminal (figure 3, part S4_A; upper switch terminal) and a ground terminal (figure 3, part S4_A; lower ground terminal); and a third switch and a fourth switch (figure 3, parts S3_A and S2_A) coupled between the switch terminal (figure 3, parts S3_A and S2_A; right switch terminal) and a power output (figure 3, parts S3_A and S2_A; left power output), each of the third switch and fourth switch having an on-resistance (figure 3, parts S3_A and S2_A; on-resistance) and the first and second switches (figure 3, parts S1_A and S4_A; on-resistance) (paragraph [0128]; the current capacity of the switching transistor in the horizontal bridge circuit is less than the current capacity of the switching transistor in the vertical bridge circuit, in other words, a specification of the switching transistor in the horizontal bridge circuit can be reduced, to reduce costs of the inverter circuit [based on Ohm Law: V=IR; R=V/I; therefore the current capacity is inversely proportional to resistance]); and a controller (figure 3, part controller generated by 112-114 [presented in figure 7]) having control outputs (figures 3 and 7, part control outputs from 113 and 114) and a feedback input (figures 3 and 7, part feedback input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit), the control outputs (figures 3 and 7, part control outputs from 113 and 114) coupled to switch control terminals of the first (figure 3, part S1_A), second (figure 3, part S4_A), third (figure 3, part S3_A), and fourth switches (figure 3, part S2_A), the controller (figure 3, part controller generated by 112-114 [presented in figure 7]) configurable to: responsive to the feedback input having a first state (figures 3 and 7, part feedback input [at first state] to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit; first state to operate between two levels), provide first modulated signals at the control outputs (figures 3 and 7, part first modulated signals at control outputs from 113 and 114) to cause the first through fourth switches (figure 3, part S1_A, S4_A, S3_A and S2_A) to provide a voltage at the power output that switches between two levels (figures 10 and 14, part voltage at the power output in Two-level working mode) (paragraph [0117]-[0122]; the MCU enters a two-level working mode); and responsive to the feedback input having a second state (figures 3 and 7, part feedback input [at second state] to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit; second state to operate between more than two levels), provide second modulated signals at the control outputs (figures 3 and 7, part second modulated signals at control outputs from 113 and 114) to cause the first through fourth switches (figure 3, part S1_A, S4_A, S3_A and S2_A) to provide a voltage at the power output that switches between more than two levels (figures 10 and 14, part voltage at the power output in Three-level working mode) (paragraph [0117]-[0122]; the MCU enters a three-level working mode).
Tang does not expressly disclose each of the third switch and fourth switch having a higher on-resistance than the first and second switches.
Hart teaches (see figures 1-10) each of the third switch and fourth switch (figure 6, part on-resistance of T3 and T2) having a higher on-resistance than the first and second switches (figure 6, part on-resistance of T1 and T4) (paragraph [0057]; the channel resistances of the Upper and Lower switches [T1 and T4] can be much lower than the channel resistances of the Mid-Lower and Mid-Upper switches [T3 and T2]. As an example, in the preferred implementation MOSFETs are used as the power switching devices, and the channel resistance of the Upper and Lower switches [T1 and T4] (i.e. the higher rated switches) may be in the region of 1.4 mΩ, and the channel resistance of the Mid-Lower and Mid-Upper switches [T3 and T2] (i.e. the lower rated switches) may be in the region of 10 mΩ).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to elect the first to the fourth switches of Tang with the first to the fourth switches features as taught by Hart, because it reduces the costs of the power converter and reduces the conduction losses (Abstract).
Regarding claim 2, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the state of the feedback input (figures 3 and 7, part feedback input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) indicates an amount of current at switch terminal (figure 3, part S1_A; lower switch terminal; through feedback input to 112 of the current output) (paragraph [0091]; a T-type three-phase full-bridge three-level inverter circuit, a switching transistor in a horizontal bridge circuit is controlled based on torque of a motor, a current output by an output terminal, a temperature of the switching transistor in the horizontal bridge circuit, and a terminal voltage of the switching transistor in the horizontal bridge circuit).
Regarding claim 3, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the state of the feedback input (figures 3 and 7, part feedback input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) indicates a temperature (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit) of the third and a fourth switches (figure 3, parts S3_A and S2_A) (paragraph [0091]; a T-type three-phase full-bridge three-level inverter circuit, a switching transistor in a horizontal bridge circuit is controlled based on torque of a motor, a current output by an output terminal, a temperature of the switching transistor in the horizontal bridge circuit, and a terminal voltage of the switching transistor in the horizontal bridge circuit).
Regarding claim 4, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the modulated signals (figures 3 and 7, part modulated signals at control outputs from 113 and 114) are at pulse width modulation signals (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13).
Regarding claim 6, claim 13 has the same limitations, except that is a method claim, based on this is rejected for the same reasons.
Regarding claim 7, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) a memory component (figures 3 and 7, part memory component inside of 112) coupled to the controller (figures 3 and 7, part controller generated by 112-114) (paragraphs [0142]-[0145]; The chip system may further include a memory. The memory is configured to store necessary program instructions and data), the memory component (figures 3 and 7, part memory component inside of 112) configurable to store a lookup table (LUT) (figures 3 and 7, part LUT at memory component inside of 112) (paragraph [0092]; looking up a table) that maps different states of the feedback input (figures 3 and 7, part feedback input to 112 of any of: temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) to different modulated signals (figures 3 and 7, part modulated signals at control outputs from 113 and 114), and the controller (figures 3 and 7, part controller generated by 112-114) is configurable to provide the modulated signals (figures 3 and 7, part modulated signals at control outputs from 113 and 114) by accessing the memory component (figures 3 and 7, part memory component inside of 112) (paragraph [0092]; The MCU 11 obtains torque of a motor or a current output by an output terminal of the MCU 11, converts one of the torque and the current (for example, converts one of the torque and the current by looking up a table) into a Q-axis current Iq and a D-axis current Id of the motor, obtains a corresponding Q-axis voltage Uq and a corresponding D-axis voltage Ud, performs further calculation to obtain a comparison value of a PWM control signal, calculates a duty cycle, controls, based on the duty cycle, a switching transistor to be conducted and cut off, converts a direct current output by a direct current power supply 12 into an alternating current, supplies power to a motor 13, and controls a voltage and a current of an output alternating current, to control a rotational speed of the motor).
Regarding claim 8, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the first and second switches are rated to support current (figure 3, parts S1_A and S4_A; rated to support current) and each having an on-resistance (RDSON) (figure 3, parts S1_A and S4_A; on-resistance) and wherein each of the third and fourth switches has an on-resistance (figure 3, parts S3_A and S2_A; on-resistance) (paragraph [0128]; the current capacity of the switching transistor in the horizontal bridge circuit is less than the current capacity of the switching transistor in the vertical bridge circuit, in other words, a specification of the switching transistor in the horizontal bridge circuit can be reduced, to reduce costs of the inverter circuit [based on Ohm Law: V=IR; R=V/I; therefore the current capacity is inversely proportional to resistance]). However, Tang does not expressly disclose the first and second switches are rated to support current to approximately 200-400 Amp and each having an on-resistance (RDSON) of approximately 2-6 mΩ and wherein each of the third and fourth switches has an on-resistance of approximately 20-40 mΩ.
Hart teaches (see figures 1-10) each of the third switch and fourth switch (figure 6, part on-resistance of T3 and T2) having a higher on-resistance than the first and second switches (figure 6, part on-resistance of T1 and T4) (paragraph [0057]; the channel resistances of the Upper and Lower switches [T1 and T4] can be much lower than the channel resistances of the Mid-Lower and Mid-Upper switches [T3 and T2]. As an example, in the preferred implementation MOSFETs are used as the power switching devices, and the channel resistance of the Upper and Lower switches [T1 and T4] (i.e. the higher rated switches) may be in the region of 1.4 mΩ, and the channel resistance of the Mid-Lower and Mid-Upper switches [T3 and T2] (i.e. the lower rated switches) may be in the region of 10 mΩ).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to elect the first to the fourth switches of Tang with the first to the fourth switches features as taught by Hart, because it reduces the costs of the power converter and reduces the conduction losses (Abstract).
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to select the first to the fourth switches of the converter circuit of the combination of Tang and Hart to meet with the first and second switches are rated to support current to approximately 200-400 Amp and each having an on-resistance (RDSON) of approximately 2-6 mΩ and wherein each of the third and fourth switches has an on-resistance of approximately 20-40 mΩ, in order to obtain more efficient and accurate power conversion based on the design requirements. Additional, the invention would perform equally well with the first to the fourth switches of the converter circuit as taught by the combination of Tang and Hart. Further, In re Aller, 105 USPQ 233 (MPEP 2144.05 (II)) discloses discovering the optimum or workable ranges involves only routine skill in the art.
Regarding claim 11, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the power converter circuit (figure 3, part power converter circuit at 11) is part of a three-phase circuit (figure 7, part Vertical bridge circuit) or is coupled to a three-phase motor circuit (figure 7, part 13) (paragraph [0093]; The MCU 11 includes a three-phase full-bridge).
Regarding claim 12, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the power converter circuit (figure 3, part power converter circuit at 11) includes a T-type converter (paragraph [0094]; the T-type three-phase full-bridge three-level inverter circuit).
Regarding claim 22, Tang and Hart teach everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the third and fourth switches (figure 3, parts S3_A and S2_A) are the only switches (figure 3, parts S3_A and S2_A) coupled between the switch terminal (figure 3, parts S3_A and S2_A; right switch terminal) and the power output (figure 3, parts S3_A and S2_A; left power output).
Regarding claim 17, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 21, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
