CTNF 18/816,768 CTNF 89701 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 7 is objected to because of the following informalities: Claim 7, second line recites “to ] access”, which appears a typographical error of -- to access --. Appropriate correction is required. 07-29-01 AIA Claim 10 is objected to because of the following informalities: Claim 10, second line recites “each power switch”, which should be -- each switch -- because in this way was previously presented this term in the claim . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim s 1-5, 8-17 and 21 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-4, 9-16 and 21 of copending Application No. 19/022,765 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because : Regarding claim 1, the copending Application discloses an apparatus comprising: a two-level converter circuit; a higher-level converter circuit, wherein the higher-level converter circuit increases a number of levels to more than two levels provided by the two-level converter circuit; and a controller configured to receive a feedback signal associated with the two-level converter circuit and the higher-level converter circuit, wherein the controller is configured to generate at least one control signal for controlling at least one switch of the two-level converter circuit based on the feedback signal, and wherein the controller is configured to generate at least another control signal for controlling at least another switch of the higher-level converter circuit based on the feedback signal (see claim 1) ; Regarding claim 2, the copending Application discloses the feedback signal is an amount of current being drawn by the two-level converter circuit and the higher-level converter circuit (see claim 2) ; Regarding claim 3, the copending Application discloses the feedback signal is associated with a temperature associated with the at least another switch of the higher-level converter circuit (see claim 3) ; Regarding claim 4, the copending Application discloses the at least one control signal is a pulse width modulation (PWM) signal (see claim 4) ; Regarding claim 5, the copending Application discloses the at least another control signal is a pulse width modulation (PWM) signal (see claim 4) ; Regarding claim 8, the copending Application discloses the at least one switch of the two-level converter circuit is rated to support current to approximately 200-400 Amp and has a resistance between drain-source when the at least one switch of the two-level converter circuit is on (RDSON) of approximately 2-6 mΩ and wherein the at least another switch of the higher-level converter circuit has RDSON of approximately 20-40 mΩ (see claim 10) ; Regarding claim 9, the copending Application discloses the controller is a pulse width modulation (PWM) unit (see claim 9) ; Regarding claim 10, the copending Application discloses the controller is configured to generate a pulse width modulation (PWM) signal associated with each power switch within the two-level converter circuit and the higher-level converter circuit (see claim 9) ; Regarding claim 11, the copending Application discloses the two-level converter circuit is a three-phase circuit (see claim 11) ; Regarding claim 12, the copending Application discloses the higher-level converter circuit is a T-type converter (see claim 12) ; Regarding claim 13, the copending Application discloses a method comprising: receiving a feedback signal associated with a multi-level converter circuit, wherein the multi-level converter circuit includes a two-level converter circuit and a higher-level converter circuit, wherein the higher-level converter circuit increases a number of levels associated with the multi-level converter circuit to more than two levels provided by the two-level converter circuit; generating at least one control signal for controlling at least one switch of the two-level converter circuit based on the feedback signal; and generating at least another control signal for controlling at least another switch of the higher-level converter circuit based on the feedback signal (see claim 13) ; Regarding claim 14, the copending Application discloses the feedback signal is a current being drawn by the multi-level converter circuit (see claim 14) ; Regarding claim 15, the copending Application discloses the feedback signal is associated with a temperature associated with the at least another switch of the higher-level converter circuit (see claim 15) ; Regarding claim 16, the copending Application discloses the at least one controls signal is a pulse width modulation (PWM) signal (see claim 16) ; Regarding claim 17, the copending Application discloses the at least another control signal is a pulse width modulation (PWM) signal (see claim 16) ; Regarding claim 21, the copending Application discloses the at least one switch of the two-level converter circuit is rated to support current to approximately 200-400 Amp and has a resistance between drain-source when the at least one switch of the two-level converter circuit is on (RDSON) of approximately 2-6 mΩ and wherein the at least another switch of the higher-level converter circuit has RDSON of approximately 20-40 mΩ (see claim 21) . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-7 and 9-20 are rejected under 35 U.S.C. 102 ( a)(1 ) as being anticipated by Tang et al. (US 2023/0104049), hereinafter Tang . Regarding claim 1, Tang discloses (see figures 1-14) an apparatus (figure 7) comprising: a two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) ; a higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) , wherein the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) increases a number of levels to more than two levels (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) provided by the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) (paragraph [0117]; When the switching transistor in the vertical bridge circuit and the switching transistor in the horizontal bridge circuit are enabled, it is equivalent to that the MCU enters a three-level working mode. When the switching transistor in the vertical bridge circuit is enabled and the switching transistor in the horizontal bridge circuit is disabled, it is equivalent to that the MCU enters a two-level working mode) ; and a controller (figure 7, part controller generated by 112-114) configured to receive a feedback signal (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) associated with the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) and the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) , wherein the controller (figure 7, part controller generated by 112-114) is configured to generate at least one control signal (figure 7, part control signal from 114) for controlling at least one switch (figure 7, part S1_A-C and S4_A-C) of the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) based on the feedback signal (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) , and wherein the controller (figure 7, part controller generated by 112-114) is configured to generate at least another control signal (figure 7, part control signal from 113) for controlling at least another switch (figure 7, part S2_A-C and S3_A-C) of the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) based on the feedback signal (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit, the current output by the output terminal or the terminal voltage of the switching transistor in the horizontal bridge circuit) (paragraph [0128]; the basis of the T-type three-phase full-bridge three-level inverter circuit, the switching transistor in the horizontal bridge circuit is enabled or disabled based on the torque of the motor, the current output by the output terminal, the temperature of the switching transistor in the horizontal bridge circuit, and the terminal voltage of the switching transistor in the horizontal bridge circuit. The switching transistor in the horizontal bridge circuit is enabled in the low-torque region, so that the MCU works in the three-level working mode, to improve system efficiency of the inverter circuit. The switching transistor in the horizontal bridge circuit is disabled in the high-torque region, to avoid a case in which all switching transistors in the three-phase full-bridge inverter circuit continuously work. In addition, the current capacity of the switching transistor in the horizontal bridge circuit is less than the current capacity of the switching transistor in the vertical bridge circuit, in other words, a specification of the switching transistor in the horizontal bridge circuit can be reduced, to reduce costs of the inverter circuit) . Regarding claim 2, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the feedback signal (figure 7, part feedback signal of the current output by the output terminal) is an amount of current being drawn (figure 7, part feedback signal of the current output by the output terminal) by the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) and the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) (paragraph [0128]) . Regarding claim 3, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the feedback signal (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit) is associated with a temperature associated (figure 7, part feedback signal of temperature of the switching transistor in the horizontal bridge circuit) with the at least another switch (figure 7, part S2_A-C and S3_A-C) of the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) (paragraph [0128]) . Regarding claim 4, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the at least one control signal (figure 7, part control signal from 114) is a pulse width modulation (PWM) signal (figure 7, part control signal from 114) (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13) . Regarding claim 5, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the at least another control signal (figure 7, part control signal from 113) is a pulse width modulation (PWM) signal (figure 7, part control signal from 113) (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13) . Regarding claim 6, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the at least one control signal (figure 7, part control signal from 114) and the at least another control signal (figure 7, part control signal from 113) cause the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) and the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) to operate in a hybrid modulation mode (paragraph [0117]; When the switching transistor in the vertical bridge circuit and the switching transistor in the horizontal bridge circuit are enabled, it is equivalent to that the MCU enters a three-level working mode. When the switching transistor in the vertical bridge circuit is enabled and the switching transistor in the horizontal bridge circuit is disabled, it is equivalent to that the MCU enters a two-level working mode. For how to enable the switching transistor in the vertical bridge circuit, the switching transistor in the vertical bridge circuit may be always enabled, or a control method shown in FIG. 9 and FIG. 10 is used to determine when to enable the switching transistor in the vertical bridge circuit. This is not limited. Unless otherwise specified, it is considered by default that the switching transistor in the horizontal bridge circuit is enabled, so that when the MCU is switched between the three-level working mode and the two-level working mode, it is considered by default that the switching transistor in the vertical bridge circuit is enabled) . Regarding claim 7, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) accessing a memory component (figure 7, part controller generated by 112-114; memory component inside of 112) (paragraphs [0142]-[0145]; The chip system may further include a memory. The memory is configured to store necessary program instructions and data) configured to store a lookup table (LUT) (figure 7, part controller generated by 112-114; LUT inside of 112) , wherein the controller (figure 7, part controller generated by 112-114) is configured to] access the LUT (figure 7, part controller generated by 112-114; LUT inside of 112) to generate the at least one control signal (figure 7, part control signal from 114) and the at least another control signal (figure 7, part control signal from 113) (paragraph [0092]; The MCU 11 obtains torque of a motor or a current output by an output terminal of the MCU 11, converts one of the torque and the current (for example, converts one of the torque and the current by looking up a table) into a Q-axis current Iq and a D-axis current Id of the motor, obtains a corresponding Q-axis voltage Uq and a corresponding D-axis voltage Ud, performs further calculation to obtain a comparison value of a PWM control signal, calculates a duty cycle, controls, based on the duty cycle, a switching transistor to be conducted and cut off, converts a direct current output by a direct current power supply 12 into an alternating current, supplies power to a motor 13, and controls a voltage and a current of an output alternating current, to control a rotational speed of the motor) . Regarding claim 9, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the controller (figure 7, part controller generated by 112-114) is a pulse width modulation (PWM) unit (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13) . Regarding claim 10, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the controller (figure 7, part controller generated by 112-114) is configured to generate a pulse width modulation (PWM) signal (figure 7, part PWM signals from 114 and 113) associated with each power switch (figure 7, part S1_A to C-S4_A to C) within the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) and the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) (paragraph [0055]; The MCU 11 controls, through PWM, the switching transistor to be conducted and cut off, converts a direct current output by the direct current power supply 12 into an alternating current, supplies power to the motor 13, and controls a voltage and a current of an output alternating current by adjusting a duty cycle of a PWM control signal, to control a rotational speed of the motor 13) . Regarding claim 11, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) is a three-phase circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) (paragraph [0093]; The MCU 11 includes a three-phase full-bridge) . Regarding claim 12, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) is a T-type converter (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) (paragraph [0094]; the T-type three-phase full-bridge three-level inverter circuit) . Regarding claim 13, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 14, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 15, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 16, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 17, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 18, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 19, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 20, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 2023/0104049), hereinafter Tang . Regarding claim 8, Tang discloses everything claimed as applied above (see claim 1). Further, Tang discloses (see figures 1-14) the at least one switch (figure 7, part S1_A-C and S4_A-C) of the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) is rated to support current (figure 7, part S1_A-C and S4_A-C) and has a resistance between drain-source when the at least one switch (figure 7, part S1_A-C and S4_A-C) of the two-level converter circuit (figure 7, part two-level converter circuit generated by Vertical bridge circuit and C1/C2) is on (RDSON) (figure 7, part RDSON of S1_A-C and S4_A-C) and wherein the at least another switch (figure 7, part S2_A-C and S3_A-C) of the higher-level converter circuit (figure 7, part higher-level converter circuit generated by Horizontal bridge circuit) has RDSON (figure 7, part RDSON of S2_A-C and S3_A-C) (paragraph [0128]; the current capacity of the switching transistor in the horizontal bridge circuit is less than the current capacity of the switching transistor in the vertical bridge circuit, in other words, a specification of the switching transistor in the horizontal bridge circuit can be reduced, to reduce costs of the inverter circuit) . However, Tang does not expressly disclose the at least one switch of the two-level converter circuit is rated to support current to approximately 200-400 Amp and has a resistance between drain-source when the at least one switch of the two-level converter circuit is on (RDSON) of approximately 2-6 mΩ and wherein the at least another switch of the higher-level converter circuit has RDSON of approximately 20-40 mΩ . It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to select the at least one switch of the two-level converter circuit and the at least another switch of the higher-level converter circuit of Tang to meet with the at least one switch of the two-level converter circuit is rated to support current to approximately 200-400 Amp and has a resistance between drain-source when the at least one switch of the two-level converter circuit is on (RDSON) of approximately 2-6 mΩ and wherein the at least another switch of the higher-level converter circuit has RDSON of approximately 20-40 mΩ, in order to obtain more efficient and accurate power conversion based on the design requirements. Additional, the invention would perform equally well with the at least one switch of the two-level converter circuit and the at least another switch of the higher-level converter circuit as disclosed Tang. Further, In re Aller, 105 USPQ 233 (MPEP 2144.05 (II)) discloses discovering the optimum or workable ranges involves only routine skill in the art. Regarding claim 21, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.O.R. / Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838 Application/Control Number: 18/816,768 Page 2 Art Unit: 2838 Application/Control Number: 18/816,768 Page 3 Art Unit: 2838 Application/Control Number: 18/816,768 Page 4 Art Unit: 2838 Application/Control Number: 18/816,768 Page 5 Art Unit: 2838 Application/Control Number: 18/816,768 Page 6 Art Unit: 2838 Application/Control Number: 18/816,768 Page 7 Art Unit: 2838 Application/Control Number: 18/816,768 Page 8 Art Unit: 2838 Application/Control Number: 18/816,768 Page 9 Art Unit: 2838 Application/Control Number: 18/816,768 Page 10 Art Unit: 2838 Application/Control Number: 18/816,768 Page 11 Art Unit: 2838 Application/Control Number: 18/816,768 Page 12 Art Unit: 2838 Application/Control Number: 18/816,768 Page 13 Art Unit: 2838 Application/Control Number: 18/816,768 Page 14 Art Unit: 2838 Application/Control Number: 18/816,768 Page 15 Art Unit: 2838 Application/Control Number: 18/816,768 Page 16 Art Unit: 2838 Application/Control Number: 18/816,768 Page 17 Art Unit: 2838
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